Gate-Lifted NMOS ESD Protection via Segmented Current Paths
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Solution Overview
Problem
Traditional grounded-gate NMOS (GGNMOS) devices are ineffective in protecting against electrostatic discharge (ESD) due to similar trigger voltages with the device to be protected, and existing solutions for reducing trigger voltage are only useful for supply protection and can cause false triggering with fast signals.
Innovation Solution
A gate-lifted NMOS ESD protection device triggered by a PNP transistor in series with a diode, which routes different levels of ESD current through a combination of diode, PNP, and NMOS transistors, forming low, medium, and high current paths, and an embedded SCR for effective ESD management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a grounded-gate NMOS (GGNMOS) device is used for ESD protection, then the device structure is simple, but the trigger voltage is near identical to the victim device making it incapable of providing effective protection
Solution Approach 1:
The ESD protection function is segmented into multiple current paths with different trigger mechanisms: a low current path through the diode and PNP transistor, a medium current path through the NMOS transistor, and a high current path through the embedded SCR. This segmentation allows each path to handle specific current levels effectively, resolving the contradiction between simple structure and effective protection capability.
Solution Approach 2:
The patent embeds multiple protection mechanisms within a single device structure. The embedded SCR is nested within the NMOS transistor structure, and the PNP transistor with diode is integrated into the same device. This nesting allows complex multi-level protection functionality while maintaining a relatively compact device structure.
2Reliability
If drain-engineered devices or Zener-diode-triggered devices are used to reduce trigger voltage, then additional process options are required, but the device complexity increases
Solution Approach 1:
The patent uses standard CMOS process-compatible structures that serve multiple functions. The PNP transistor and diode combination provides both voltage clamping and current steering functions, while the NMOS transistor with embedded SCR provides both medium and high current protection. This multi-functionality reduces the need for additional specialized process options while achieving effective trigger voltage reduction.
3Reliability
If gate-coupled, gate-driven, or PNP-triggered solutions are used for VT1 reduction, then additional circuitry is required, but false triggering occurs with fast signals
Solution Approach 1:
The patent applies different trigger characteristics to different current paths within the device. The diode-PNP path provides a higher trigger voltage threshold that is less susceptible to fast signal false triggering, while the NMOS-SCR path provides lower trigger voltage for effective ESD protection. This local differentiation of trigger qualities allows the device to distinguish between genuine ESD events and fast signal transitions.
Solution Approach 2:
The PNP transistor and diode combination acts as an intermediary mechanism that mediates between the input signal and the NMOS transistor. This intermediary provides a controlled trigger path that prevents direct coupling of fast signals to the NMOS gate, thereby reducing false triggering while still enabling effective ESD protection when needed.
4Device complexity
If traditional GGNMOS devices are used, then the device structure is simple, but the protection is ineffective due to similar trigger voltages with the victim device
Solution Approach 1:
The ESD protection function is segmented into multiple current paths with different trigger mechanisms: a low current path through the diode and PNP transistor, a medium current path through the NMOS transistor, and a high current path through the embedded SCR. This segmentation allows each path to handle specific current levels effectively, resolving the contradiction between simple structure and effective protection capability.
Solution Approach 2:
The patent embeds multiple protection mechanisms within a single device structure. The embedded SCR is nested within the NMOS transistor structure, and the PNP transistor with diode is integrated into the same device. This nesting allows complex multi-level protection functionality while maintaining a relatively compact device structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively handles various ESD current levels, providing robust protection with a higher trigger voltage and reduced false triggering, suitable for 5-V mobile applications up to 85°C, and demonstrates superior long-pulse TLP characteristics compared to traditional GGNMOS and FBPNP+DP devices.
Implementation Method 1
receiving a low energy current portion of an ESD pulse at an PNP transistor, conducting the low energy current portion of the ESD pulse to an output pad through a diode
Implementation Method 2
receiving a medium energy current portion of the ESD pulse at the PNP transistor, conducting the medium energy current portion of the ESD pulse to the output pad through an NMOS transistor
Implementation Method 3
receiving a high energy current portion of an ESD pulse at the PNP transistor and conducting the high energy current portion of the ESD pulse to the output pad through a silicon controlled rectifier (SCR) formed from the PNP transistor and the NMOS transistor
Data Source
AI summary
An ESD protection device including a PNP transistor connected to an input pad, a diode connected to the PNP transistor and connected to an output pad, and an NMOS transistor connected to the PNP transistor and the output pad, wherein the diode, PNP transistor, and NMOS transistor are configured to route different levels of an electrostatic discharge (ESD) current pulse from the input pad to the output pad.