Gate Line Drive Circuit Segmentation and Boosting
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Solution Overview
Problem
Existing gate line drive circuits suffer from waveform distortion due to increased inductor and capacitor loading, leading to improper signal transmission as the number of transmission stages increases, especially when transitioning from four-phase to two-phase signal duration, resulting in breakdown of the gate line drive circuit.
Innovation Solution
A gate line drive circuit design that separates and independently drives the gate line from the next-stage gate line drive circuit, utilizing multiple transistors and a boosting capacitor to maintain accurate timing control and increase current flow, allowing for shorter rising and falling times and improved display quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Illumination intensity
If the output signal duration is reduced from four-phase (4H) to two-phase (2H) to improve display quality, then the display quality is improved, but the voltage of the control node cannot be maintained due to leakage current, causing waveform distortion and circuit breakdown
Solution Approach 1:
The patent segments the gate line drive circuit into multiple independent stages, with each stage having its own control node and transistor. This segmentation allows the circuit to maintain stability in each stage while achieving the desired short pulse width, preventing the cumulative waveform distortion that occurs in multi-stage transmission.
Solution Approach 2:
The patent applies preliminary charging to the control node before the pulse output. By pre-charging the control node to a high voltage level, the circuit ensures that even with leakage current during the shortened pulse duration, the control node voltage remains sufficient to drive the transistor properly, preventing waveform distortion.
2Quantity of substance
If multiple TFTs are connected to the gate line to increase loading capacity, then the gate line can drive more pixels, but the inductor and capacitor loading increases, causing waveform distortion and signal transmission failure
Solution Approach 1:
The patent divides the gate line drive into multiple stages, with each stage driving a portion of the gate lines. This segmentation reduces the loading burden on each individual drive stage, preventing waveform distortion while still enabling the system to drive a large number of TFTs across all stages.
Solution Approach 2:
The patent introduces a control node as an intermediary between the clock signal and the gate line output. This control node acts as a buffer that isolates the loading effects from the clock signal, allowing the circuit to drive multiple TFTs without the clock signal experiencing waveform distortion.
3Measurement precision
If the clock signal duration is shortened to two-phase (2H) to improve timing precision, then the timing control accuracy is improved, but the control node voltage cannot be boosted to the required second high voltage level due to leakage current
Solution Approach 1:
The patent pre-charges the control node to a high voltage level before the pulse output. This preliminary charging ensures that when the clock signal is applied during the shortened two-phase duration, the control node already has sufficient voltage to overcome leakage current and reach the required second high voltage level for proper transistor switching.
Solution Approach 2:
The patent changes the voltage parameters of the control node by applying different voltage levels at different times. The control node is charged to a first high voltage level initially, then boosted to a second high voltage level during the pulse output. This parameter change allows the circuit to maintain adequate voltage levels even with the shortened two-phase clock signal duration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances display quality by preventing waveform distortion, allowing for more precise timing control and increased current flow, thus maintaining stable signal transmission across multiple stages.
Implementation Method 1
a boosting capacitor, wherein the first terminal of the boosting capacitor is connected to the control node
Data Source
AI summary
A gate line drive circuit includes first, second and third transistors, and a boosting capacitor. The first transistor has a control terminal connected to a charge/discharge control signal of a previous-stage gate line drive circuit, a first terminal, and a second terminal connected to a control node. The second transistor has a control terminal connected to the control node, a first terminal, and a second terminal connected to a first timing signal. The third transistor has a control terminal connected to the control node, a first terminal, and a second terminal connected to a second timing signal. The boosting capacitor has one terminal connected to the control node, and the other terminal connected to the first terminal of the third transistor and a control terminal of a first transistor of a next-stage gate line drive circuit. The first terminal of the second transistor is connected to a gate line.