Gate Line Driver Circuit Power Consumption and Reliability

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Solution Overview

Problem

Existing display apparatuses using complementary circuit structures with OS and LTPS transistors face issues such as increased power consumption and transistor deterioration due to insufficient signal degradation to the L level.

Innovation Solution

A display apparatus with a gate line driver circuit that includes a unit circuit comprising specific configurations of p-channel and n-channel transistors, where the n-channel transistor includes an oxide semiconductor and the p-channel transistors include silicon-based semiconductor layers, to enhance signal control and reduce power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If a complementary circuit structure with OS and LTPS transistors is used, then power consumption is reduced, but transistor reliability deteriorates due to insufficient signal degradation

Engineering Contradiction:
Improvepower consumptionVSAvoidtransistor reliability
Core Design Contradiction:
Loss of energyVSReliability

Solution Approach 1:

A level restoration circuit is introduced as an intermediary component between the signal input and the complementary transistors. This circuit includes a capacitor connected between the signal input node and ground, and a pull-up transistor that restores the signal level to a high level when it drops below the threshold. This intermediary mechanism ensures reliable transistor switching while maintaining the low power consumption benefits of the complementary structure.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The level restoration circuit provides beforehand cushioning by proactively restoring the signal level before it can cause unreliable transistor operation. The capacitor charges in advance to maintain the high level, and the pull-up transistor activates when the signal drops, preventing the harmful effect of insufficient signal degradation from occurring in the first place.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

2Loss of energy

If a complementary circuit structure is used, then power consumption is reduced, but circuit complexity increases

Engineering Contradiction:
Improvepower consumptionVSAvoidcircuit complexity
Core Design Contradiction:
Loss of energyVSDevice complexity

Solution Approach 1:

The level restoration circuit is merged with the existing complementary circuit structure by integrating the pull-up transistor and capacitor into the same circuit block. The restoration circuit shares the signal input node and works cooperatively with the complementary transistors, combining multiple functions into a unified circuit design that reduces overall complexity despite adding functionality.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The level restoration circuit serves multiple functions: it restores signal levels, prevents premature transistor switching, and works cooperatively with both the pull-down and pull-up transistors in the complementary structure. This multi-functionality reduces the need for separate dedicated circuits, thereby managing complexity while enhancing reliability.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS20250111829A1Display apparatus
Publication Date: 2025.04.03 SEMICON ENERGY LAB CO LTD
  • US20250111829A1 patent drawing
  • US20250111829A1 patent drawing
  • US20250111829A1 patent drawing

AI summary

A novel display apparatus is provided. The display apparatus includes first to fifth p-channel transistors and an n-channel transistor. A gate of the fifth p-channel transistor and a gate of the n-channel transistor which operate at the same timing are connected to different nodes. A gate of the first p-channel transistor is directly connected to the gate of the n-channel transistor. The gate of the fifth p-channel transistor is electrically connected to the gate of the first p-channel transistor through a source and a drain of the third p-channel transistor.