Gate Line-End Recess Filling to Preserve Metal Gate Height
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Solution Overview
Problem
The current semiconductor fabrication processes, particularly for CMOS transistors, face challenges in maintaining the height of metal gates during the formation of gate line-end regions due to the need for chemical mechanical polishing (CMP) procedures, which add complexity and cost, and require initial gate stacks with higher aspect ratios.
Innovation Solution
A process is developed where a dielectric material, such as silicon monoxide or silicon oxynitrocarbide, is used to fill the gate line-end recess without altering the height of the metal gate, allowing for the formation of a dielectric layer that is structurally functional and compatible with contact processes, eliminating the need for a CMP operation that would otherwise change the gate height.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a CMP procedure is performed after gate line-end formation to planarize the surface, then the surface flatness is improved, but the gate height is reduced and fabrication complexity increases
Solution Approach 1:
The gate line-end formation is performed before the contact hole etching process, allowing the recess to be created in advance. This preliminary action enables subsequent steps to proceed without requiring additional CMP operations, as the gate structure is already prepared for the contact formation process.
Solution Approach 2:
The CMP procedure is completely removed from the fabrication process flow. Instead of performing CMP after gate line-end formation, the process uses direct etching and filling operations that achieve the desired result without the planarization step, thereby eliminating the associated complexity and cost.
2Manufacturing precision
If a CMP procedure is performed after gate line-end formation, then the surface is planarized, but additional fabrication cost and complexity are incurred
Solution Approach 1:
The CMP procedure is completely removed from the fabrication process flow. Instead of performing CMP after gate line-end formation, the process uses direct etching and filling operations that achieve the desired result without the planarization step, thereby eliminating the associated complexity and cost.
3Manufacturing precision
If the gate stack is initially formed with higher height to compensate for CMP removal, then the gate height loss is compensated, but the aspect ratio increases and process complexity increases
Solution Approach 1:
The gate line-end formation is performed before the contact hole etching process, allowing the recess to be created in advance. This preliminary action enables subsequent steps to proceed without requiring additional CMP operations, as the gate structure is already prepared for the contact formation process.
Solution Approach 2:
Instead of forming a higher gate stack and then removing material through CMP, the process inverts the approach by forming the gate at the desired final height and creating the recess through selective etching. This eliminates the need for over-building the gate structure and subsequent material removal.
4Manufacturing precision
If the gate stack is initially formed with higher height to compensate for CMP removal, then the gate height loss is compensated, but dimension restrictions are imposed
Solution Approach 1:
The gate line-end formation is performed before the contact hole etching process, allowing the recess to be created in advance. This preliminary action enables subsequent steps to proceed without requiring additional CMP operations, as the gate structure is already prepared for the contact formation process.
Solution Approach 2:
Instead of forming a higher gate stack and then removing material through CMP, the process inverts the approach by forming the gate at the desired final height and creating the recess through selective etching. This eliminates the need for over-building the gate structure and subsequent material removal.
Data Source
AI summary
The current disclosure provides a semiconductor fabrication method that defines the height of gate structures at the formation of the gate structure. A gate line-end region is formed by removing a portion of a gate structure. A resulted recess is filled with a dielectric material is chosen to have a material property suitable for a later contact formation process of forming a metal contact. A metal contact structure is formed through the recess filling dielectric layer to connect to a gate structure and/or a source/drain region.