Gate Line Fabrication for Open Defect Detection

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Solution Overview

Problem

Conventional designs for gate lines in liquid crystal display panels using charge sharing technology fail to detect open defects before panel fabrication is complete, leading to scrapped panels and poor display quality.

Innovation Solution

The method involves forming separated and electrically isolated first and second gate lines, performing an open-short test to identify and repair any abnormalities, and then connecting the first gate line at each row to the second gate line at an adjacent row using a conductive pattern through via holes in an insulating layer, ensuring both lines receive the same gate signal.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If two gate lines are connected together after photolithography and etching process, then the fabrication process is simplified, but open defects cannot be detected before panel assembly

Engineering Contradiction:
Improvefabrication processVSAvoiddefect detection capability
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent applies preliminary action by performing open-short tests on gate lines before they are connected during the fabrication process. Specifically, the test is conducted after photolithography and etching but before the connection step, allowing defects to be detected and repaired in advance. This prevents defective panels from proceeding to assembly, thereby improving reliability without significantly complicating the overall fabrication process.

Inventive Principle:
Principle #10Preliminary action

2Productivity

If gate lines are tested after panel fabrication is complete, then all fabrication steps can proceed without interruption, but defective panels are identified too late causing scrapping

Engineering Contradiction:
Improvefabrication continuityVSAvoidpanel quality
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent implements preliminary action by moving the open-short test to an intermediate stage in the fabrication process, specifically after photolithography and etching but before gate line connection and panel assembly. This timing allows the fabrication process to continue uninterrupted through critical steps while still enabling defect detection early enough to prevent scrapping of defective panels later in production.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent applies the skipping principle by rapidly performing the open-short test at the optimized fabrication stage and immediately proceeding to connection and assembly. This minimizes the interruption to fabrication continuity while ensuring that any defective panels are quickly identified and handled, preventing them from wasting subsequent production resources.

Inventive Principle:
Principle #21Skipping (Rushing through)

3Productivity

If one gate line is broken and not detected, then the panel can be assembled, but horizontal bright or dark lines appear reducing display quality

Engineering Contradiction:
Improveassembly rateVSAvoiddisplay quality
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The patent applies preliminary action by conducting open-short tests on gate lines before panel assembly, ensuring that broken or defective gate lines are identified and repaired in advance. This prevents the formation of horizontal bright or dark lines on the display that would occur if defective panels were assembled, thereby maintaining high display quality without significantly impacting assembly rate.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS8922534B2System for display images and fabrication method thereof
Publication Date: 2014.12.30 INNOLUX CORP
  • US8922534B2 patent drawing
  • US8922534B2 patent drawing
  • US8922534B2 patent drawing

AI summary

A system for displaying images including a display panel and a fabrication method thereof are provided. The method includes forming a first gate line and a second gate line at each row of pixels of the display panel, wherein the first gate lines and the second gate lines are separated and electrically isolated from each other. A first insulating layer is formed to cover the first gate lines and the second gate lines, and a plurality of via holes are formed in the first insulating layer to expose the first gate lines and the second gate lines. Then, a first conductive pattern is formed on the first insulating layer, such that the first gate line at each row of the pixels is electrically connected to the second gate line at an adjacent row of the pixels, by the first conductive pattern, through the via holes.