Gate Line Inactivation Detection for LCD Timing Control
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Solution Overview
Problem
Conventional image display apparatuses face challenges in preventing display errors while maintaining operational margin when the delay time of gate line driving signals is large, and existing solutions either increase costs or compromise display accuracy.
Innovation Solution
An image display apparatus is designed with a gate line driving circuit, source driver, and inactivation transition detecting circuit, where a latch circuit updates display data upon gate line inactivation, and a controller measures delay time to adjust clock and start pulse timings, ensuring accurate signal updating even with delayed gate line driving signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the pulse widths of clock signals are narrowed to prevent overwriting of pixels, then display accuracy is improved, but the driving abilities are lowered and operational margin is reduced
Solution Approach 1:
The patent implements a delay detection circuit that measures the delay time of gate line driving signals and feeds this information back to the clock signal generation circuit. This feedback mechanism allows the system to dynamically adjust clock signal parameters based on actual delay conditions, preventing overwriting errors while maintaining sufficient operational margin without permanently narrowing pulse widths.
Solution Approach 2:
The patent changes the timing parameters of clock signals and start pulses based on detected delay time. By adjusting the start timing and pulse widths dynamically according to measured delay conditions, the system achieves accurate pixel writing without permanently reducing operational margin, resolving the contradiction between precision and reliability.
2Manufacturing precision
If a gate line inactivation detecting circuit is provided to prevent overwriting, then display accuracy is improved, but costs are increased
Solution Approach 1:
The patent merges the delay detection function with the existing gate line driving circuit by utilizing the same signal paths and components. The delay detection circuit is integrated into the gate line driving architecture, sharing resources with the pixel driving functions, thereby preventing overwriting errors without significantly increasing overall circuit complexity or cost.
Solution Approach 2:
The patent designs the delay detection circuit to serve multiple purposes: it detects delay time for timing adjustment, characterizes gate line driving performance, and provides feedback for optimizing display accuracy. This multi-functional approach reduces the need for separate dedicated circuits, lowering overall system complexity while maintaining improved display precision.
3Manufacturing precision
If delay time detection circuit is provided outside the display apparatus, then display accuracy is improved, but costs are increased
Solution Approach 1:
The patent integrates the delay time detection circuit directly into the display apparatus structure, combining it with the gate line driving circuit and pixel array. This integration eliminates the need for external delay detection equipment, reducing system complexity and cost while maintaining the ability to achieve high display accuracy through internal delay measurement and compensation.
Data Source
AI summary
For an image display apparatus, cost reduction is enabled to prevent display errors while ensuring operational margin to prevent display errors even when the delay time of gate line driving signals is large. A source driver of a liquid-crystal display apparatus includes a data latch circuit for supplying display data to a decode circuit. A gate line inactivation transition detecting circuit detects inactivation of each of a plurality of gate lines and activates a detect signal for a certain period with that timing. The data latch circuit updates the held display data in response to activation of the detect signal.