Gate Signal Line Overlap Layout for Uniform Pixel Kickback
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Solution Overview
Problem
Misalignment during the formation of conductive layers in display devices leads to non-uniform capacitances between pixel rows, resulting in uneven kickback voltages and reduced display quality due to visible stains.
Innovation Solution
The display device incorporates a specific configuration of gate signal lines and connection patterns, where the upper gate signal line overlaps the lower gate signal line in an overlapping area, maintaining constant capacitance and preventing stains by ensuring uniform kickback voltages across pixel rows.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the conductive layers are formed using conventional mask alignment methods, then the manufacturing process is simple, but the capacitances between pixel rows become non-uniform resulting in kickback voltage variations and display stains
Solution Approach 1:
The patent applies local quality by creating an overlapping configuration between the upper gate signal line and lower gate signal line specifically in the overlapping area. This localized structural modification ensures that the capacitance between pixel rows remains uniform in the critical overlapping region, thereby preventing kickback voltage variations and display stains without requiring complete redesign of the entire device structure
Solution Approach 2:
The patent implements the nesting principle by positioning the upper gate signal line to overlap with the lower gate signal line, creating a nested arrangement where one signal line is positioned above and partially overlaps another. This nested configuration ensures consistent capacitance values across pixel rows by maintaining uniform electrical characteristics in the overlapping area, thus resolving the capacitance uniformity issue
2Manufacturing precision
If the mask alignment is not precisely controlled, then the manufacturing process remains fast and simple, but the conductive layers become misaligned causing non-uniform capacitances and display defects
Solution Approach 1:
The patent applies beforehand cushioning by designing a structure where the upper gate signal line overlaps with the lower gate signal line in advance. This pre-configured overlapping structure compensates for potential mask alignment variations during manufacturing, ensuring that capacitance uniformity is maintained even when alignment tolerances are not perfectly controlled, thus preventing display stains without requiring extremely tight manufacturing tolerances
Solution Approach 2:
The patent utilizes parameter changes by modifying the geometric configuration of the gate signal lines - specifically, creating an overlapping arrangement where the upper gate signal line and lower gate signal line intersect in a defined overlapping area. This structural parameter change ensures that the electrical characteristics (capacitance) remain uniform across pixel rows, compensating for alignment variations and maintaining display quality
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration ensures consistent kickback voltages across pixel rows, enhancing display quality by maintaining uniform capacitance between the gate signal lines and connection patterns, thereby preventing stains and improving overall display performance.
Implementation Method 1
capacitances between the conductive layers of pixel rows may not be uniform, therefore, kickback voltages of the pixel rows may not be uniform
Data Source
AI summary
A display device includes a first transistor including a gate electrode, a second transistor including a lower gate electrode, an upper gate electrode, and a first end portion electrically connected to an end portion of the first transistor, a lower gate signal line extending in a first direction, an upper gate signal line disposed on the lower gate signal line and extending in a first direction, and a first connection pattern disposed on the upper gate signal line, electrically connecting the gate electrode and a second end portion of the second transistor, and intersecting the lower gate signal line and the upper gate signal line. An entirety of the upper gate signal line overlaps a part of the lower gate signal line in an overlapping area in which the lower gate signal line or the upper gate signal line overlaps the first connection pattern.