Gate Line Dielectric Plug Layout for Dense FinFET Scaling
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Solution Overview
Problem
Current semiconductor fabrication processes face challenges in scaling to the 10 nanometer node or smaller, due to variability in conventional methods, which limits the integration of new technologies and the fabrication of functional components for future technology nodes.
Innovation Solution
The implementation of pitch quartering and merged fin pitch quartering approaches in integrated circuit structure fabrication, along with the use of multi-layer trench isolation and fin trim isolation techniques, to enhance transistor density and maintain desirable fin stress for improved carrier mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication processes are used for scaling, then manufacturing simplicity is maintained, but manufacturing precision deteriorates due to variability at 10 nanometer node or smaller
Solution Approach 1:
The fabrication process is divided into multiple discrete stages including forming first and second trenches at different depths, selective epitaxial growth in specific regions, and staged doping processes. This segmentation allows each step to be optimized independently for precision while maintaining overall process manageability at the 10 nanometer node
Solution Approach 2:
Different regions of the semiconductor structure receive different treatments: merged fin regions undergo specific stress engineering while non-merged fins maintain standard processing. The epitaxial growth is performed selectively in certain regions but not others, and doping concentrations are varied by location. This local quality approach enables precise control of electrical properties and stress states in different areas to achieve the required manufacturing precision
2Productivity
If transistor density is increased through pitch quartering, then productivity improves, but manufacturing precision becomes more difficult to maintain due to process variability
Solution Approach 1:
Stress engineering is performed preliminarily during the epitaxial growth stage before subsequent processing steps. The fin stress is engineered into the structure during controlled epitaxial growth in specific regions, establishing the desired stress state early in the process when the structure is still being formed, which helps maintain precision even as density increases through pitch quartering
Solution Approach 2:
The process utilizes parameter changes including varying epitaxial growth conditions, adjusting doping concentrations in different regions, and modifying trench depths to control fin stress. These parameter adjustments enable precise control of stress states while achieving high transistor density through pitch quartering methodologies
3Manufacturing precision
If multi-layer trench isolation and fin trim isolation are implemented, then manufacturing precision improves for fin stress control, but device complexity increases
Solution Approach 1:
The isolation structure utilizes vertical dimensionality with multi-layer trenches at different depths rather than only lateral differentiation. First trenches extend to a first depth and second trenches extend to a greater second depth, creating a three-dimensional isolation architecture that provides precise fin stress control while managing the complexity through vertical stratification rather than horizontal proliferation of structures
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
These techniques enable the fabrication of advanced integrated circuits with increased transistor density and improved performance by allowing precise control of fin stress and isolation, addressing the limitations of conventional methods in scaling to smaller node sizes.
Implementation Method 1
a first region is subjected to epitaxial growth to form a first semiconductor layer
Implementation Method 2
a first doping process is performed by ion implantation to implant a first dopant into the second semiconductor layer
Data Source
AI summary
Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first silicon fin having a longest dimension along a first direction. A second silicon fin having a longest dimension is along the first direction. An insulator material is between the first silicon fin and the second silicon fin. A gate line is over the first silicon fin and over the second silicon fin along a second direction, the second direction orthogonal to the first direction, the gate line having a first side and a second side, wherein the gate line has a discontinuity over the insulator material, the discontinuity filled by a dielectric plug.