Gate Line Reduction in Double Rate Driving Displays
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Solution Overview
Problem
The application of the double rate driving type (DRD) in high-resolution electroluminescence display apparatuses leads to an increase in the number of gate lines, which results in insufficient design area, increased bezel size, and limited panel design.
Innovation Solution
The electroluminescence display apparatus incorporates a sensing device with a sensing channel terminal connected to a pixel through a sensing line, and a power terminal for a reference voltage, where sampling switches are alternately turned on to reduce the number of gate lines by sharing gate control signals among pixels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If double rate driving type is applied to high-resolution display, then data line reduction and manufacturing cost reduction are achieved, but the number of gate lines increases by twice
Solution Approach 1:
The gate driver is divided into multiple segments (first gate driver, second gate driver, third gate driver) that can independently control different groups of pixels. This segmentation allows the system to manage the increased number of gate lines through modular control, reducing the complexity burden on any single driver unit while maintaining the DRD configuration.
Solution Approach 2:
The gate lines are designed to serve multiple functions: they control both the selection of pixels and the timing of data input for internal compensation. By making gate lines multi-functional, the system reduces the total number of gate lines needed compared to a design where separate control lines would be required for each function, thereby mitigating the gate line increase problem while maintaining DRD operation.
2Adaptability or versatility
If number of gate lines increases, then double rate driving with internal compensation is enabled, but design area becomes insufficient and bezel area increases
Solution Approach 1:
Adjacent gate lines are merged into shared control lines that can be simultaneously or sequentially activated. For example, the first and second gate lines can be controlled by a common first gate driver, reducing the number of independent driver units needed. This merging approach reduces the overall gate driver area while maintaining the ability to provide independent control for internal compensation operations.
Solution Approach 2:
The patent utilizes time-divisional control in the temporal dimension to manage spatial constraints. By controlling different pixel groups at different time intervals through shared gate lines, the system effectively increases the functional capacity without proportionally increasing the physical area of gate drivers, thus preserving design area while enabling internal compensation.
3Device complexity
If gate driver circuit size increases, then more gate lines can be controlled, but mounting area increases and panel design is limited
Solution Approach 1:
The gate driver functionality is segmented into multiple independent driver units (first gate driver, second gate driver, third gate driver) that can be distributed across the panel. This segmentation reduces the circuit size of any single driver unit and allows for flexible placement and mounting, improving panel design flexibility while maintaining comprehensive gate control capability.
Solution Approach 2:
The gate driver system is designed with dynamic control capabilities where different gate lines can be activated at different times and for different durations. This dynamic approach allows the same physical infrastructure to support varying control requirements, reducing the need for oversized static driver circuits and enabling more flexible panel designs that can adapt to different display configurations.
Data Source
AI summary
An electroluminescence display apparatus includes a first pixel, a second pixel disposed adjacent to the first pixel in a horizontal direction to share a data line to which a first data voltage and a second data voltage are time-divisionally supplied and a reference voltage line to which a reference voltage is supplied, along with the first pixel, a first gate line coupled to the first pixel to transfer a first gate control signal, corresponding to the reference voltage, to the first pixel, a second gate line coupled to the first and second pixels in common to transfer a second gate control signal, corresponding to the first data voltage and the reference voltage in common, to the first and second pixels, and a third gate line coupled to the second pixel to transfer a third gate control signal, corresponding to the second data voltage, to the second pixel.