Gate Line Segmentation for Pixel Interference Reduction
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Solution Overview
Problem
Existing display devices, such as active matrix LCDs and OLEDs, face interference issues between pixels due to the layout of gate and data lines, which can affect image quality and manufacturing costs, particularly with the high expense of data driving IC chips.
Innovation Solution
The display device incorporates a unique arrangement of gate and data lines, where each pair of gate lines is positioned between two adjacent pixel rows, with the first gate line closer to the pixel row and supplied with voltage earlier than the second, reducing electromagnetic interference by routing connections between the first and second gate lines from the data lines, and using two adjacent gate lines to be supplied with voltage simultaneously.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If gate lines are arranged in conventional layout, then manufacturing cost is reduced, but interference between pixels increases affecting image quality
Solution Approach 1:
The gate line arrangement is segmented into multiple pairs of gate lines (first gate lines and second gate lines) where each pair is disposed between adjacent pixel rows. This segmentation allows independent control and routing of signals to different pixel rows, reducing electromagnetic interference between adjacent pixels while maintaining manageable device complexity through systematic organization.
Solution Approach 2:
Data lines serve as intermediaries that are routed between the first and second gate lines to connect to switching elements. This intermediary routing arrangement separates the paths of gate signals and data signals, reducing cross-talk and interference between pixels while enabling efficient signal transmission without increasing overall device complexity.
2Object-affected harmful factors
If data lines are routed between gate lines, then interference between pixels is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The routing arrangement implements local quality by positioning data lines specifically between the first and second gate lines in regions where interference is most problematic. This localized routing optimization reduces electromagnetic interference in critical areas without requiring high-precision routing across the entire display device, thereby balancing interference reduction with manufacturing feasibility.
3Speed
If first gate line is supplied with voltage earlier than second gate line, then pixel switching speed is improved, but energy consumption increases
Solution Approach 1:
The gate driver supplies voltages to the first and second gate lines in a periodic sequence, where the first gate line receives voltage earlier than the second gate line. This periodic sequential activation enables faster pixel switching by staggered activation while managing energy consumption through controlled timing rather than continuous high-power delivery to all lines simultaneously.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This arrangement minimizes interference between gate lines and pixels, improving image quality without increasing the number of IC chips, thus reducing manufacturing costs and enhancing display performance.
Implementation Method 1
a plurality of pairs of first and second gate lines connected to the switching elements, transmitting a gate-on voltage for turning on the switching elements
Implementation Method 2
each pair of first and second gate lines is disposed between two adjacent pixel rows and is connected to one of the pixel rows
Data Source
AI summary
A display device according to an exemplary embodiment of the present invention includes: a plurality of pixels including switching elements; a plurality of pairs of first and second gate lines connected to the switching elements and separated from each other, transmitting a gate-on voltage for turning on the switching elements; and a plurality of data lines connected to the switching elements, transmitting data signals, wherein each pair of first and second gate lines is disposed between two adjacent pixel rows and is connected to one of the pixel rows.