Active-Matrix Substrate Gate Line Segmentation for High-Speed Driving
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Solution Overview
Problem
Existing display technologies face challenges in driving gate lines at high speed due to potential dullness issues, which increases the load on gate lines and makes it difficult to reduce the width of the picture frame region effectively.
Innovation Solution
The solution involves arranging gate drivers and switching elements within the pixel regions of the active-matrix substrate, allowing for the control of potential on gate lines through control signals, reducing dullness and enabling high-speed driving while minimizing the picture frame width.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If gate drivers are arranged along one side of the active-matrix substrate, then the width of the picture frame region is reduced, but the routing distance of gate lines increases causing potential dullness
Solution Approach 1:
The gate line routing is segmented into multiple paths by introducing intermediate connection points and alternative routes. This segmentation allows the gate line signal to be distributed through multiple shorter segments rather than one long continuous path, reducing the cumulative resistance and capacitance that cause potential dullness while maintaining the compact driver arrangement.
Solution Approach 2:
The gate line routing transitions from a primarily one-dimensional linear path to a two-dimensional distributed network. By utilizing vertical connections and intermediate distribution points, the routing architecture adds a dimensional aspect that shortens individual signal paths while achieving comprehensive coverage, thereby reducing RC delays and potential degradation.
2Area of stationary object
If gate line routing distance is increased to reduce picture frame width, then device compactness is improved, but gate line driving speed decreases due to increased load
Solution Approach 1:
Intermediate connection points and distribution nodes are introduced as mediators in the gate line routing architecture. These intermediaries act as local signal distribution centers that reduce the effective routing distance from the main driver to individual gate lines, thereby maintaining driving speed while achieving compact overall layout.
Solution Approach 2:
The gate line system is divided into multiple segmented routes with intermediate connection points. This segmentation creates multiple shorter signal paths instead of one long path, reducing the total resistance and capacitance that limit switching speed, thus maintaining high driving speed in a compact configuration.
Data Source
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AI summary
A technique is provided that reduces dullness of a potential provided to a line such as gate line on an active-matrix substrate to enable driving the line at high speed and, at the same time, reduces the size of the picture frame region. On an active-matrix substrate (20a) are provided gate lines (13G) and source lines. On the active-matrix substrate (20a) are further provided: gate drivers (11) each including a plurality of switching elements, at least one of which is located in a pixel region, for supplying a scan signal to a gate line (13G); and lines (15L1) each for supplying a control signal to the associated gate driver (11). A control signal is supplied by a display control circuit (4) located outside the display region to the gate drivers (11) via the lines (15L1). In response to a control signal supplied, each gate driver (11) drives the gate line (13G) to which it is connected.