Gate Line Shift Register Feedback to Prevent Concurrent Switching
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Solution Overview
Problem
Existing gate line driving devices in liquid crystal displays suffer from signal delays and interference, leading to concurrent switching on of gate lines, which results in image quality issues due to insufficient signal stability and synchronized clock signals.
Innovation Solution
A shift register design incorporating thin film transistors, capacitors, feedback modules, and switch modules that output intermediate signals as feedback and trigger signals, reducing load-driven delays and eliminating the need for synchronized clock signals, thereby maintaining signal stability and reserving spare time between gate line driving operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the output of one stage of shift register is used as the trigger signal of another stage of shift register, then the gate line driving function is achieved, but signal delay occurs and two sequential rows of gate lines are concurrently switched on
Solution Approach 1:
The patent introduces an intermediate signal as a mediator between the output signal and the trigger signal. The intermediate signal is generated by an intermediate signal generation module that receives the output signal and produces a delayed version of it. This intermediate signal then triggers the next stage of the shift register, preventing the direct connection that causes signal delay and concurrent gate line switching. The intermediate signal acts as a buffer that decouples the timing relationship between stages.
2Productivity
If the output of one stage of shift register is used as the trigger signal of another stage of shift register, then the shifting function is achieved, but the pixel array generates interference with the output terminal
Solution Approach 1:
The intermediate signal generation module serves as an intermediary that isolates the pixel array from directly affecting the output terminal. By using the intermediate signal (which is a processed version of the output signal) to trigger the next stage, the patent prevents the pixel array's interference from being directly fed back into the shift register output. The intermediate signal acts as a filter that blocks harmful interference while maintaining the necessary triggering function.
3Extent of automation
If clock signals CLK, CLKB are triggered synchronously with the output, then the shift register operates in sync, but no reserved spare time is left between driving operations
Solution Approach 1:
The patent applies preliminary action by generating the intermediate signal in advance before it is needed to trigger the next stage. The intermediate signal generation module continuously processes the output signal to create the intermediate signal, so that when the triggering moment arrives, the intermediate signal is already ready and stable. This preliminary preparation ensures that there is sufficient time margin between operations, preventing concurrent switching while maintaining synchronized operation.
4Ease of operation
If the duty ratio for clock signals is maintained as 50%, then synchronous triggering is achieved, but two continuous rows of gate lines are concurrently switched on
Solution Approach 1:
The intermediate signal acts as a mediator that decouples the clock signal duty ratio from the gate line switching timing. Instead of directly using the clock signal to control the switching of gate lines, the patent uses the intermediate signal (which has its own timing characteristics) to trigger the shift register stages. This allows the clock signal to maintain its simple 50% duty ratio for ease of operation, while the intermediate signal ensures proper timing separation to prevent concurrent switching, thus maintaining reliability.
Data Source
AI summary
It discloses a shift register and a gate line driving device, relating to the technology field for a liquid crystal display, it is made to reduce the switching on errors for gate lines and improve the quality of the image. Said shift register includes: a first thin film transistor, a second thin film transistor, a third thin film transistor, a storage capacitor, a feedback module, and a switch module, wherein said feedback module is used to receive a trigger signal of the feedback module of the previous stage and a clock signal in order to pull up the level of the first node Qa as a pull up node, and to output a feedback signal to the shift register of the previous stage and output a trigger signal to the feedback module of the next stage, said switch module is used to maintain the output terminal of the shift register of the present stage at a low level when the shift register of the present stage does not operate. An embodiment of the present invention is applied to a liquid crystal display panel.