Replacement Gate Liner Expansion Control for Stable FinFET Gate CD
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Solution Overview
Problem
In the semiconductor industry, the fabrication of metal gate structures for fin field effect transistors (Fin FETs) faces challenges due to the expansion of silicon-based liners during thermal processing, which affects the gate critical dimension (CD) and electrical performance by creating gaps between the liner and the interlayer dielectric layer, leading to reduced gate CD and potential performance issues.
Innovation Solution
A method involving the formation of a silicon-based liner over sidewall spacers, followed by thermal treatment that converts the liner into oxide, reducing gaps and stabilizing the gate CD by allowing the liner to occupy the voids formed by interlayer dielectric shrinkage, thereby improving the semiconductor device's electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a liner is used in the gate structure during annealing processes, then stresses are reduced and gaps are filled, but the gate critical dimension (CD) changes due to liner expansion and shrinkage
Solution Approach 1:
The patent applies parameter changes by carefully controlling the liner thickness within specific ranges (e.g., 5-15 nm) and adjusting annealing process parameters (temperature, time, atmosphere) to optimize the balance between stress reduction and gate CD stability. By changing these parameters, the liner's expansion and shrinkage effects are managed to minimize gate CD variation while maintaining stress reduction benefits.
Solution Approach 2:
The patent employs composite material structures by combining the liner material (such as silicon oxide, silicon nitride, or silicon oxynitride) with the gate dielectric and metal gate layers. This composite approach allows the liner to provide stress reduction and gap filling functions while the overall structure maintains dimensional stability through the combined properties of different materials.
2Stability of the object's composition
If the liner expands during annealing to fill gaps, then voids are reduced, but the gate CD changes adversely
Solution Approach 1:
The patent controls the liner expansion behavior by adjusting annealing parameters (temperature, time, gas atmosphere) and liner thickness to achieve optimal gap filling while limiting excessive expansion that would alter gate CD. Specific parameter ranges are established to balance void reduction with dimensional stability.
Solution Approach 2:
The patent applies partial action by using a liner thickness that is sufficient to fill gaps and reduce voids but not so thick as to cause excessive expansion and gate CD variation. The liner dimensions are optimized to provide just enough expansion to fill voids without over-expanding and affecting gate critical dimensions.
3Stability of the object's composition
If gate spaces with funnel or V-shaped profiles are formed, then gap filling is enhanced and voids are reduced, but the manufacturing process complexity increases
Solution Approach 1:
The patent applies curvature by forming gate spaces with funnel or V-shaped profiles instead of straight vertical walls. This curved geometry enhances gap filling during subsequent deposition processes and reduces void formation. The curved profiles are achieved through controlled etching processes that create the desired non-linear sidewall shapes.
Solution Approach 2:
The patent uses preliminary action by pre-forming the funnel or V-shaped gate space profiles before depositing the liner and subsequent layers. This preliminary geometric preparation ensures that subsequent materials conformally fill the gate spaces and reduces void formation, simplifying later processing steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces the gate CD variability and enhances the electrical performance of semiconductor devices by controlling the expansion of the silicon-based liner, ensuring consistent and improved device performance.
Implementation Method 1
forming a silicon based liner over the sidewall spacers; thermally treating the silicon based liner and the first insulating layer, and thereby causing a reduction in a volume of the first insulating layer and an increase in a volume of the silicon based liner
Data Source
AI summary
A method of manufacturing a semiconductor device includes forming a dummy gate structure over a substrate. The dummy gate structure has a dummy gate dielectric layer and a dummy gate electrode layer. Sidewall spacers including one or more layers of insulating materials are formed on sidewalls of the dummy gate structure. A silicon based liner is formed over the sidewall spacers. A first insulating layer is formed over the silicon based liner. The silicon based liner and the first insulating layer are thermally treating causing a reduction in a volume of the first insulating layer and an increase in a volume of the silicon based liner. The dummy gate structure is removed to form a gate space in the first insulating layer. The gate space is formed with a high-k dielectric layer and a first conductive layer.