Gate Electrode Liner Structure for Threshold-Stable Semiconductor Cells
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Solution Overview
Problem
The miniaturization of semiconductor devices is hindered by the formation of gate electrodes wider than the element regions, leading to deviations in position and affecting the stability and efficiency of semiconductor devices.
Innovation Solution
A semiconductor device design featuring a semiconductor layer with a convex element region, a gate electrode covered by a liner layer, and element separation portions on both sides, where the liner layer extends from the gate electrode to the separation portions, ensuring precise alignment and reducing threshold value fluctuations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the gate electrode is formed larger in width than the element region to reduce position deviation, then the positional stability of the gate electrode is improved, but the device area increases and miniaturization is hindered
Solution Approach 1:
The patent introduces a vertical dimension solution by forming the gate electrode to protrude from the surface of the insulating layer covering the element region. This three-dimensional configuration allows the gate electrode to maintain adequate width for positional stability while reducing its planar footprint, thereby enabling device miniaturization without sacrificing manufacturing precision
Solution Approach 2:
The gate electrode is segmented into multiple regions with different widths: a wider portion for positional stability and a narrower protruding portion for miniaturization. This segmentation allows the gate electrode to simultaneously satisfy both the requirement for reduced position deviation and the requirement for reduced device area
2Reliability
If the gate electrode width is increased to ensure proper coverage, then the reliability of the semiconductor device is improved, but the device complexity and manufacturing difficulty increase
Solution Approach 1:
The gate electrode is configured to protrude vertically from the insulating layer surface, creating a three-dimensional structure that maintains adequate coverage width for reliability while reducing the need for excessively complex planar patterns. This vertical extension simplifies the manufacturing process by reducing alignment complexity between the gate electrode and element region
3Ease of manufacture
If the gate electrode is formed with larger width to account for position deviation, then the manufacturing robustness is improved, but the threshold value stability deteriorates due to increased area
Solution Approach 1:
The protruding gate electrode configuration reduces the effective planar area of the gate electrode while maintaining its vertical coverage, thereby stabilizing the threshold value by reducing capacitance effects and area-dependent variations, while the adequate width portion maintains manufacturing robustness
Solution Approach 2:
The gate electrode is designed with different width characteristics in different locations: a wider base portion for manufacturing robustness and a narrower protruding portion for threshold value stability. This local quality variation allows simultaneous optimization of both manufacturing ease and electrical performance
Data Source
AI summary
According to one embodiment, a semiconductor device includes a semiconductor layer, an element region provided on the semiconductor layer convexly, having a predetermined width in a first direction along a surface of the semiconductor layer, and extending in a second direction along the surface of the semiconductor layer and intersecting the first direction, a gate electrode arranged above the element region, a liner layer covering the gate electrode, and an element separation portion extends in the second direction on both sides of the element region in the first direction, and the liner layer continuously extends from the gate electrode to the element separation portion and the liner layer in the element separation portion lies below the element separation portion.