Gate Structures With Liners To Prevent Height Loss
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Solution Overview
Problem
As semiconductor processes scale down, fabricating gate structures becomes challenging due to critical dimension scaling and process limitations, leading to gate height loss and potential shorts between gate and source/drain contacts.
Innovation Solution
The use of liners and insulator fills during interlevel dielectric fill and planarization processes to preserve gate height, combined with a Si fill and additional liner deposition, prevents gate height loss and allows for the formation of a larger gate cap that isolates source and drain metallization features.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gate structures are fabricated using conventional processes during scaling, then manufacturing is simpler, but gate height loss occurs leading to shorts between gate and source/drain contacts
Solution Approach 1:
A liner is deposited on the sidewall spacers before the interlevel dielectric fill process. This preliminary action protects the sidewall spacers from damage during subsequent processing steps, preventing gate height loss that would otherwise occur during conventional fabrication processes.
Solution Approach 2:
The liner acts as an intermediary protective layer between the sidewall spacers and the interlevel dielectric material. It mediates the interaction by preventing direct contact and potential damage from the dielectric fill process, thereby maintaining gate height without requiring complete process redesign.
2Reliability
If a larger gate cap is formed to prevent shorts, then electrical reliability improves, but manufacturing precision requirements increase
Solution Approach 1:
The liner is deposited in advance on the sidewall spacers before gate cap formation. This preliminary protection ensures that the sidewall spacers maintain their dimensions and position, providing a stable foundation for forming the larger gate cap with improved precision and reduced variability.
Solution Approach 2:
The liner provides beforehand cushioning protection to the sidewall spacers, compensating for potential damage that would occur during processing. This cushioning effect maintains the structural integrity and dimensional stability of the spacers, enabling more precise gate cap formation.
Data Source
AI summary
The present disclosure generally relates to semiconductor structures and, more particularly, to gate structures and methods of manufacture. The structure includes: a plurality of gate structures comprising a gate cap, sidewall spacers and source and drain regions; source and drain metallization features extending to the source and drain regions; and a liner extending along an upper portion of the sidewall spacers of at least one of the plurality of gate structures.