Gate Mask Layer Formation Using Spacer-Defined Dummy Lines
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Solution Overview
Problem
Current semiconductor processing techniques, such as Self Aligned Double Patterning (SADP), face challenges in meeting the demands of ever-increasing gate pitch scaling and footprint reduction while ensuring process reliability, particularly in forming mask layers for transistor devices with fin structures.
Innovation Solution
A method involving the formation of a mandrel above a semiconductor fin structure, followed by the deposition of spacers and filler materials to create a mask layer, allowing for direct patterning and subsequent processing without relying on multiple patterning processes, enabling improved etch resistance and chemical-mechanical polishing (CMP) capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If Self Aligned Double Patterning (SADP) is used to form patterns beyond optical limitations, then gate critical dimension can be reduced, but process complexity and risk of hard mask damage increase
Solution Approach 1:
The patent segments the patterning process into distinct stages: forming a mandrel, depositing first spacers, removing mandrel, depositing second spacers, and forming the mask layer. This segmentation allows each step to be optimized independently, reducing overall process complexity while achieving the desired critical dimension
Solution Approach 2:
The mandrel is formed in advance as a sacrificial structure that defines the position of subsequent spacers. This preliminary action enables direct patterning without requiring multiple patterning cycles, simplifying the overall process while maintaining precision
2Manufacturing precision
If multiple patterning processes are used to define gate critical dimension, then sub-resolution pitch patterns can be achieved, but the hard mask is at risk of being damaged or over etched
Solution Approach 1:
The patent introduces spacers as intermediary structures that transfer the pattern from the mandrel to the final mask layer. These spacers act as protective intermediaries, allowing the mask layer to be formed after spacer processing is complete, thereby avoiding direct exposure and potential damage to the hard mask during recessing operations
Solution Approach 2:
The mask layer is formed in advance before the spacer recessing step. This preliminary action ensures the mask layer is not exposed to the harsh etching conditions used during spacer processing, protecting it from damage while still enabling precise critical dimension control through the spacer-defined pattern
3Adaptability or versatility
If the mask layer is formed early in the process, then it can be used for multiple patterning steps, but it must be designed to withstand process requirements that may compromise its performance in subsequent steps
Solution Approach 1:
The mask layer is formed in advance as a preliminary structure that defines the gate pattern. This early formation allows it to serve as the foundation for subsequent spacer deposition, while its position in the process stack enables it to be engineered specifically for its final function rather than being constrained by earlier process requirements
4Device complexity
If direct patterning is used instead of multiple patterning, then process complexity is reduced, but achieving sub-resolution pitch patterns becomes more difficult
Solution Approach 1:
The patent transitions from planar patterning to three-dimensional spacer-based patterning. By depositing conformal spacers on the mandrel and using their thickness to define the critical dimension, the process achieves sub-resolution patterns through vertical dimension control rather than lateral optical resolution, enabling direct patterning to achieve precision previously requiring multiple patterning steps
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables scalable gate critical dimension definition without multiple patterning, reduces the risk of hard mask damage, and allows for a mask layer designed specifically for subsequent processing steps, enhancing etch resistance and CMP performance.
Implementation Method 1
providing a first spacer material on the mandrel, thereby forming a first set of spacers including a first spacer at a first side surface of the mandrel
Implementation Method 2
providing a second spacer material on the first and the second spacers, thereby forming a second set of spacers arranged at the side surfaces of the first set of spacers
Implementation Method 3
etching a top portion of the first filler material to form recesses between the second set of spacers
Implementation Method 4
allowing for a mask layer designed without taking process requirements related to the forming of the spacers into account. Instead, the mask layer may be engineered with respect to requirements associated with subsequent processing of the gate structures, such as for example replacement dummy gate processing. In particular, the mask layer may be adapted to have an improved etch resistance and/or be an improved chemical-mechanical polishing (CMP) stopping layer
Data Source
Figure 1A~2B
Figure 3A~4B
Figure 5A~6B
AI summary
A method for forming a mask layer (190) above a semiconductor fin structure (100) is disclosed. The method comprises forming a first set of spacers and a second set of spacers (131, 132, 133, 134) arranged at the side surfaces of the first set of spacers, providing a first filler material (140) between the second set of spacers, etching a top portion of the first filler material to form recesses (150) between the second set of spacers, and providing a second filler material (160) in the recesses, the second filler material forming a set of dummy mask lines. Further, the method comprises recessing a top portion (170) of at least the first set of spacers, providing a mask layer material (180) between the dummy mask lines, and removing the dummy mask lines and the first filler material.