Multi-Stage Gate Mask Etching for High-Aspect-Ratio Gate Cuts
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Solution Overview
Problem
As integrated circuits shrink in size, forming high aspect ratio gate cuts in semiconductor devices becomes challenging due to issues with tapering and incomplete break-through of the gate mask structure, affecting device isolation and density.
Innovation Solution
A plasma etching process with a multi-stage approach is used to form gate cuts with a high aspect ratio, employing finely-tuned passivation and etching cycles to maintain verticality and selectivity, along with a gate masking structure to ensure consistent mask break-through and minimize tapering.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a single-stage etch process is used to form gate cuts, then the manufacturing process is simpler and faster, but the aspect ratio is limited and tapering occurs
Solution Approach 1:
The etch process is divided into multiple stages with different etch chemistries and parameters. Each stage targets specific depth ranges and material layers, enabling precise control over the high aspect ratio gate cut formation while avoiding excessive tapering that would occur in a single-stage process.
Solution Approach 2:
The etch process dynamically adjusts parameters including gas flow rates, RF power, pressure, and temperature across different stages. This dynamic control allows optimization of etch rate and selectivity at each depth range, achieving the required aspect ratio while managing process complexity.
2Manufacturing precision
If etching depth is increased to achieve higher aspect ratio, then device isolation is improved, but tapering increases and mask break-through becomes inconsistent
Solution Approach 1:
The first etch stage performs preliminary excavation to reach a target depth before subsequent stages complete the breakthrough. This staged approach ensures consistent mask removal while maintaining vertical sidewalls, preventing the tapering and inconsistency that occur with single-stage deep etching.
Solution Approach 2:
Etch parameters such as gas composition, pressure, and power are changed between stages to optimize performance at different depths. The first stage uses parameters optimized for initial etching, while subsequent stages adjust parameters to maintain verticality and achieve clean breakthrough, ensuring reliability.
3Productivity
If device spacing is reduced to increase density, then integration density is improved, but gate cut formation becomes more challenging
Solution Approach 1:
The multi-stage etch process provides local quality control by applying different etch chemistries and parameters to different spatial regions and depth ranges. This enables precise formation of gate cuts even at reduced device spacing, maintaining manufacturing precision while supporting higher integration density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The process achieves gate cuts with a height-to-width aspect ratio of 5:1 or higher, reducing manufacturing costs by 25-35% and improving device integration density with minimal tapering and optimal selectivity.
Implementation Method 1
A plasma etching process with a multi-stage approach is used to form gate cuts with a high aspect ratio
Implementation Method 2
employing finely-tuned passivation and etching cycles to maintain verticality and selectivity
Data Source
AI summary
Techniques are described to form semiconductor devices that include one or more gate cuts having a very high aspect ratio (e.g., an aspect ratio of 5:1 or greater). A semiconductor device includes a conductive material that is part of a transistor gate structure around or otherwise on a semiconductor region. The gate structure may be interrupted between two transistors with a gate cut that extends through an entire thickness of the gate structure. A plasma etching process may be performed to form the gate cut with a very high height-to-width aspect ratio with little to no tapering in its sidewall profile, so as to enable densely integrated devices. Furthermore, an etching process may be performed on a gate masking structure used to pattern the location of the gate cuts to ensure that the gate masking structure has low sidewall taper and sufficiently opened enough to expose the underlying gate.