Gate Mask Layer Structure for Seam-Free GAA Transistor Integration
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Solution Overview
Problem
The integration of multi-gate devices in semiconductor manufacturing is challenging due to increased complexity and the need for advanced processes that improve gate control and reduce short-channel effects while maintaining low-power and high-performance requirements.
Innovation Solution
The formation of gate-all-around transistor structures using a bottom-up process, such as ALD, for the gate and source/drain mask layers, which eliminates seams or voids, allowing for improved semiconductor structure performance by ensuring seamless mask layers and enhanced integration of semiconductor structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional top-down processes are used to form gate and source/drain mask layers, then the manufacturing process is simpler, but seams or voids are formed in the mask layers reducing device performance
Solution Approach 1:
The patent applies bottom-up deposition processes instead of conventional top-down patterning to form the gate and source/drain mask layers. This inversion of the manufacturing approach allows the mask layers to be formed from the substrate upward, eliminating the formation of seams or voids that occur with top-down methods, while maintaining process feasibility through atomic layer deposition (ALD) techniques
Solution Approach 2:
The patent changes the deposition parameters and methodology from conventional top-down patterning to bottom-up atomic layer deposition. This parameter change enables the formation of seamless mask layers by controlling the deposition process to grow the material conformally from the substrate surface upward, fundamentally altering how the mask layers are formed to eliminate structural defects
2Reliability
If multi-gate devices are integrated to improve gate control, then gate-channel coupling is increased, but fabrication integration becomes more challenging
Solution Approach 1:
The patent segments the fabrication process into distinct bottom-up deposition steps for forming the gate and source/drain mask layers separately. This segmentation allows each layer to be optimized independently through controlled ALD deposition, managing the fabrication complexity while achieving the required gate control for multi-gate devices
Solution Approach 2:
The bottom-up deposition process enables self-aligned formation of the gate and source/drain structures. The conformal deposition from the substrate upward automatically positions features relative to each other, providing self-alignment that simplifies the integration of multi-gate devices without requiring complex additional alignment steps
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the performance of semiconductor structures by preventing issues caused by seams or voids in mask layers, leading to better electrical isolation and reliability of semiconductor devices.
Implementation Method 1
The gate mask layer is formed by a bottom-up process, such as ALD process. In addition, the S/D mask layer is formed by a bottom-up process, such as ALD process
Data Source
AI summary
Semiconductor structures and methods for forming the same are provided. The semiconductor structure includes a gate structure formed over a substrate, and a source/drain (S/D) structure formed adjacent to the gate structure. The semiconductor structure includes a gate spacer formed adjacent to the gate structure, and an etching stop layer adjacent to the gate spacer. The semiconductor structure also includes a gate mask layer formed over the gate structure, and a topmost surface of the gate mask layer is higher than a top surface of the etching stop layer.