Gate Material Segmentation for Channel Strain Engineering
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Solution Overview
Problem
Current methods for engineering strain in the channel region of field-effect-transistors, such as stress liners and embedded silicon germanium, are limited in effectively enhancing carrier mobility and device performance, necessitating further improvements in stress application techniques.
Innovation Solution
A method involving the use of a first gate material with a Young's modulus less than 130 GPa, such as Si0.8Ge0.2 or Ge, is applied, followed by forming a stress liner, removing a portion of the gate, and filling the opening with a second gate material of higher Young's modulus to enhance stress transfer to the channel region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stress or pressure
If a gate material with low Young's modulus (less than 130 GPa) is used, then stress relaxation and strain application to the channel region is improved, but gate structural strength and stability deteriorate
Solution Approach 1:
The gate structure is divided into two segments: a first gate material layer (less than 130 GPa) for stress relaxation and a second gate material layer (greater than or equal to 130 GPa) for structural support. This segmentation allows each layer to fulfill its specific function without compromise.
Solution Approach 2:
The gate is constructed as a composite structure combining two different gate materials with distinct Young's modulus values. The composite design enables the low-modulus material to provide stress relaxation while the high-modulus material provides structural strength, resolving the contradiction between these two requirements.
2Productivity
If stress liners are applied to enhance carrier mobility, then device performance is improved, but process complexity and manufacturing difficulty increase
Solution Approach 1:
The patent extracts and removes the stress liner layer after the gate material has been deposited. By taking out the stress liner after it has served its purpose of enabling low-modulus gate material deposition, the process avoids the complexity of maintaining stress liners through subsequent manufacturing steps while still achieving the desired carrier mobility enhancement.
3Stress or pressure
If embedded silicon germanium stressors are used in source/drain regions, then strain effectiveness is improved, but manufacturing precision and process control difficulty increase
Solution Approach 1:
The low-modulus gate material acts as an intermediary that transfers and distributes stress more effectively to the channel region compared to conventional embedded stressors. This intermediary approach achieves strain effectiveness without requiring precise control of stressor placement and dimensions in the source/drain regions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively applies and retains strain in the channel region, improving carrier mobility and device performance by optimizing stress distribution and relaxation, even in the absence of traditional stress liners.
Implementation Method 1
applying stress liners. A compressive stress liner is normally applied to a PFET transistor
Implementation Method 2
engineering of strain in the channel region of field-effect-transistors
Implementation Method 3
The first gate material may have a Young's modulus value being smaller than 130 GPa, preferably smaller than 115 GPa, and more preferably smaller than 100 GPa
Data Source
AI summary
There is disclosed a method of applying stress to a channel region underneath a gate of a field-effect-transistor, which includes the gate, a source region, and a drain region. The method includes steps of embedding stressors in the source and drain regions of the FET; forming a stress liner covering the gate and the source and drain regions; removing a portion of the stress liner, the portion of the stress liner being located on top of the gate of the FET; removing at least a substantial portion of the gate of a first gate material and thus creating an opening therein; and filling the opening with a second gate material.