Selective Metal Caps on Gate Work Functions for Lower Resistance
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Solution Overview
Problem
As semiconductor devices scale down, gate resistance increases, adversely impacting device performance such as speed, which existing technologies have not adequately addressed.
Innovation Solution
The method involves depositing n-type and p-type work function layers over a gate dielectric layer, forming a dielectric capping layer to protect the n-type work function, and selectively applying metal caps directly on these layers to reduce gate resistance, using techniques like ALD and selective etching to ensure precise deposition.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If device geometry is scaled down to increase functional density, then production efficiency increases and costs decrease, but gate resistance increases adversely impacting device performance
Solution Approach 1:
The patent applies local quality by creating asymmetric gate structures where different regions of the gate have different properties. Specifically, the gate electrode has varying thickness across its width, with thicker regions positioned over source/drain regions to reduce contact resistance, while thinner regions are maintained over the channel to preserve gate control. This localized variation in gate thickness optimizes both electrical performance and scaling compatibility.
Solution Approach 2:
The patent implements nesting by integrating multiple functional elements within the gate structure. The gate electrode is nested within a gate dielectric layer, which is itself nested within a gate contact structure. Additionally, the asymmetric gate design nests thicker and thinner regions within the same gate electrode to simultaneously achieve low resistance and good control.
2Reliability
If gate electrode thickness is increased to reduce gate resistance, then electrical conductivity improves, but gate control over the channel deteriorates
Solution Approach 1:
The patent resolves this contradiction by applying local quality through asymmetric gate thickness design. The gate electrode thickness is locally increased in specific regions (over source/drain) to improve conductivity, while locally maintained at thinner dimensions in other regions (over channel) to preserve gate control. This spatially varying thickness profile optimizes both electrical performance and control characteristics.
Solution Approach 2:
The patent applies dimensionality change by transitioning from a uniform two-dimensional gate thickness to a three-dimensional varying thickness profile. The gate electrode thickness becomes a function of position across the gate width, allowing independent optimization of electrical conductivity and gate control in different spatial regions within the same structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces gate resistance, improving device performance by enhancing gate-channel coupling and reducing off-state current, while being compatible with existing fabrication processes.
Implementation Method 1
depositing a conductive cap layer over the top surface of the p-type work function layer and over the top surface of the n-type work function layer
Data Source
AI summary
A semiconductor structure and a method of forming the same are provided. In an embodiment, an exemplary semiconductor structure includes a gate structure. The gate structure includes a gate dielectric layer, an n-type work function layer embedded in the gate dielectric layer, a dielectric capping layer embedded in the n-type work function layer, and a p-type work function layer embedded in the dielectric capping layer. A top surface of the gate structure exposes the n-type work function layer, the dielectric capping layer, and the p-type work function layer. The semiconductor structure also includes a first metal cap on the n-type work function layer and a second metal cap on the p-type work function layer. The first metal cap is spaced apart from the second metal cap. without formed on the dielectric capping layer.