Semiconductor Gate Metal Impurity Adsorption Layer
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Solution Overview
Problem
The existing manufacturing process for semiconductor devices results in high contact resistance between the metal gate and gate contact due to voids formed in the glue layer, primarily caused by impurities like fluorine reacting with titanium in the glue layer during annealing.
Innovation Solution
A manufacturing method is introduced that involves forming an impurity adsorption layer on the gate metal layer, followed by an annealing treatment to absorb impurities, and subsequent removal of the adsorption layer, reducing the impurity content in the metal gate and preventing impurities from entering the glue layer, thereby minimizing void formation and enhancing contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the gate metal layer is deposited to fill the opening, then the metal gate structure is formed, but impurity is introduced into the gate metal layer which subsequently enters the glue layer during annealing
Solution Approach 1:
The impurity adsorption layer serves as a mediator that decouples the gate metal layer from the glue layer during annealing. It allows the gate structure to be formed with standard deposition processes while intercepting impurities before they can contaminate the glue layer, thus maintaining manufacturing simplicity while improving interface quality.
Solution Approach 2:
The impurity adsorption layer extracts and removes harmful impurities (such as fluorine) from the metal gate during annealing treatment. By taking out these impurities and concentrating them in the adsorption layer, the glue layer interface is protected from contamination, and the impurities are subsequently removed together with the adsorption layer.
2Ease of manufacture
If a glue layer is formed on the contact holes, then the contact structure is prepared, but voids form in the glue layer between the metal gate and gate contact due to impurity reaction
Solution Approach 1:
The impurity adsorption layer is positioned as an intermediary between the metal gate and the glue layer. During annealing, it captures impurities that would otherwise diffuse into the glue layer and create voids. This maintains the simplicity of forming a continuous glue layer while preventing defect formation at the critical gate interface.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method effectively reduces impurity content in the metal gate, eliminating voids in the glue layer and improving contact resistance between the metal gate and gate contact, leading to enhanced device performance.
Implementation Method 1
performing a first annealing treatment on a semiconductor structure on which the impurity adsorption layer has been formed, to make the impurity in the gate metal layer enter the impurity adsorption layer
Implementation Method 2
depositing a gate metal layer on the semiconductor structure to fill the opening
Data Source
AI summary
The present disclosure discloses a manufacturing method for a semiconductor apparatus, and relates to the field of semiconductor technologies. Forms of the method include: providing a semiconductor structure, where the semiconductor structure includes: a substrate and an interlayer dielectric layer on the substrate, where the interlayer dielectric layer has an opening for forming a gate; depositing a gate metal layer on the semiconductor structure to fill the opening, where the gate metal layer contains impurity; forming an impurity adsorption layer on the gate metal layer; performing a first annealing treatment on a semiconductor structure on which the impurity adsorption layer has been formed, to make the impurity in the gate metal layer enter the impurity adsorption layer; and removing the impurity adsorption layer after the first annealing treatment is performed. The present disclosure may reduce impurity in the gate metal layer, thereby improving contact resistance of the gate and improving device performance.