Gate Metal Passivation Layer for CMP Dishing
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Solution Overview
Problem
In semiconductor manufacturing, the thinning of aluminum metal gates during chemical-mechanical polishing leads to increased metal gate resistance, dishing effects, and threshold voltage mismatch in I/O devices, causing chip malfunctions due to over-polishing and uneven metal gate thickness.
Innovation Solution
A method involving a treatment process to transform a metal layer into a passivation layer on top and a gate metal layer on bottom before chemical-mechanical polishing, ensuring the passivation layer remains in trenches and preventing dishing effects, while maintaining the thickness of the gate metal layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Shape
If chemical-mechanical polishing is performed on the metal gate to planarize the surface, then surface flatness is improved, but metal gate thickness is reduced causing dishing effects and increased gate resistance
Solution Approach 1:
A protective layer is formed over the metal gate before chemical-mechanical polishing. This preliminary protective structure prevents the metal gate from being over-polished, thereby preventing dishing effects and maintaining uniform metal gate thickness while still achieving surface planarization.
Solution Approach 2:
The protective layer acts as an intermediary between the CMP process and the metal gate. It absorbs the polishing action and protects the underlying metal gate from excessive material removal, thus preventing dishing while allowing the surface to be planarized.
2Use of energy by moving object
If aluminum thickness is reduced to lower power consumption, then power consumption is improved, but metal gate resistance increases causing device characteristic changes
Solution Approach 1:
The invention changes the physical and chemical parameters of the metal gate surface by forming a protective layer and controlling the CMP process. This maintains the optimal aluminum thickness for low power consumption while preventing the dishing effects that would otherwise increase gate resistance and alter device characteristics.
3Shape
If chemical-mechanical polishing is performed on low pattern density areas, then surface planarization is improved, but dishing occurs due to over-polishing
Solution Approach 1:
The protective layer is applied in advance to counteract the harmful polishing effect. It pre-shields the metal gate in low pattern density areas from over-polishing, thereby preventing dishing effects while still allowing overall surface planarization to occur.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution prevents dishing effects, improves I-V characteristics, and ensures matching threshold voltages for paired devices, thereby preventing chip malfunctions and maintaining electrical characteristics.
Implementation Method 1
A treatment process is performed to transform the remaining portion of the metal layer into a passivation layer on the top portion and a gate metal layer on the bottom portion
Implementation Method 2
A chemical-mechanical polishing process is performed until the first dielectric layer is exposed so that a remaining portion of the passivation layer remains in the trench
Data Source
AI summary
A semiconductor device and a method for manufacturing the same. The method includes steps hereinafter. A substrate is provided with a first dielectric layer thereon. The first dielectric layer is provided with a trench. Then, a metal layer is formed to fill the trench and to cover the surface of the first dielectric layer. The metal layer is partially removed so that a remaining portion of the metal layer covers the first dielectric layer. A treatment process is performed to transform the remaining portion of the metal layer into a passivation layer on the top portion and a gate metal layer on the bottom portion. A chemical-mechanical polishing process is performed until the first dielectric layer is exposed so that a remaining portion of the passivation layer remains in the trench.