Gate Metal Patterning for Tight Pitch CMOS Devices
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Solution Overview
Problem
Current gate metal patterning techniques face challenges in selectively removing gate metal from one region (pFET or nFET) while protecting the other region, especially in tight pitch applications like 7 nm nodes and beyond, which can lead to undesirable gate metal loss and device failure.
Innovation Solution
A method involving a first gate metal layer deposition over both pFET and nFET regions, followed by a masking process to protect one region during etching, allowing for partial removal of the gate metal from the other region, and subsequent sealing and removal of the remaining metal, enabling the deposition of a second gate metal layer with a different work function value.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a mask is used to protect one region during etching, then selective gate metal removal is achieved, but gate metal loss occurs in the exposed region
Solution Approach 1:
A seal layer is deposited over the exposed gate metal layer before the etching process. This preliminary action prevents etchant from reaching and removing the gate metal in the exposed region, thereby eliminating gate metal loss while still allowing selective removal in the masked region.
Solution Approach 2:
The seal layer acts as an intermediary protective barrier between the etchant and the gate metal layer. It selectively protects the gate metal in regions where the mask is removed, allowing precise control over where gate metal is removed without unintended loss.
2Manufacturing precision
If etching is performed to remove gate metal from one region, then threshold voltage control is achieved, but device failure occurs due to excessive metal loss
Solution Approach 1:
The seal layer is deposited in advance to protect gate metal regions that should not be removed. This preliminary protective action prevents excessive metal loss that would lead to device failure, while still allowing controlled etching in regions where threshold voltage adjustment is desired.
Solution Approach 2:
The process converts the potential harm of uncontrolled etching into a benefit by using the seal layer to define precise etch boundaries. The seal layer transforms what would be harmful gate metal loss into a controlled process that achieves threshold voltage tuning without compromising device reliability.
3Reliability
If dual metal gates are used for pFET and nFET regions, then transistor performance is improved, but fabrication complexity increases
Solution Approach 1:
The gate metal layer is segmented into different regions with different properties. The first gate metal layer has uniform composition initially, then selective removal and seal layer deposition create regions with different effective gate metal compositions, enabling different threshold voltages for pFET and nFET without requiring completely separate deposition processes.
Solution Approach 2:
Different regions of the gate structure are given different local qualities through selective seal layer deposition. The sealed regions retain the first gate metal composition while unsealed regions receive different treatment, creating local variations in gate properties that optimize performance for specific transistor types without increasing overall fabrication complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively controls transistor threshold voltage and facilitates the fabrication of dense nanosheet transistor arrays, ensuring compatible CMOS processing without excessive gate metal loss.
Implementation Method 1
The first structure is subjected to an etching process, thereby removing a first portion of the first gate metal layer from between the mask and the substrate
Implementation Method 2
a mask covering the first FET structure
Implementation Method 3
forming a second gate metal layer on the first and second FET structures
Data Source
AI summary
Gate metal patterning techniques enable the incorporation of different work function metals in CMOS devices such as nanosheet transistor devices, vertical FETs, and FinFETs. Such techniques facilitate removal of gate metal from one region of a device without damage from over-etching to an adjacent region. The fabrication of CMOS devices with adjoining nFET/pFET gate structures and having very tight gate pitch is also facilitated. The techniques further enable the fabrication of CMOS devices with adjoining gate structures that require relatively long etch times for removal of gate metal therefrom, such as nanosheet transistors. A nanosheet transistor device including dual metal gates as fabricated allows tight integration.