Semiconductor Gate And Metal Strip Layout for Dense Routing Access
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The design of integrated circuits faces challenges in routing resources due to complex process rules, particularly in advanced processes, which hinders achieving smaller chip areas and better performance.
Innovation Solution
The solution involves a novel design where gate strips and metal strips are configured in a crisscross pattern, with specific pitch ratios, allowing for increased pin access points and improved routing resources, enabling reduced chip area and enhanced performance by utilizing double patterning techniques in photolithography operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional routing design is used in advanced processes, then manufacturing complexity is reduced, but routing resources are insufficient and chip area increases
Solution Approach 1:
The patent introduces a third metal layer (M3) stacked vertically above the first metal layer (M1), transforming the routing problem from a two-dimensional plane to a three-dimensional structure. This vertical stacking provides additional routing pathways without increasing the horizontal chip footprint, effectively increasing routing resources while maintaining or reducing chip area.
Solution Approach 2:
The patent implements nested conductive structures where plug structures are formed within contact holes that penetrate through dielectric layers, and metal layers are stacked within vertical columns. This nesting approach maximizes the use of vertical space for routing, providing multiple routing levels within a compact footprint, thereby increasing routing capacity without proportionally increasing chip area.
2Adaptability or versatility
If complex process rules are followed, then manufacturing precision is maintained, but routing flexibility is reduced
Solution Approach 1:
The patent divides the routing function across multiple separate metal layers (M1, M2, M3) and dielectric layers, with each layer serving specific routing purposes. This segmentation allows different process rules to be applied to different layers independently, maintaining manufacturing precision for each layer while collectively providing enhanced routing flexibility through the stacked architecture.
Solution Approach 2:
The patent introduces intermediary structures such as contact holes and plug structures that mediate between different metal layers. These intermediaries enable vertical interconnections while allowing each metal layer to be manufactured and controlled independently according to its specific process requirements, thus maintaining precision while enabling flexible routing across layers.
3Productivity
If pin access points are increased, then performance is improved, but chip area increases
Solution Approach 1:
The patent enables additional pin access points by utilizing the vertical dimension through stacked metal layers. Contact holes and plug structures provide vertical access to upper metal layers, allowing pins to access routing resources in three dimensions rather than only on the surface plane. This increases pin access ability without requiring proportional increases in horizontal chip area.
Data Source
AI summary
A method of manufacturing a semiconductor device, including: forming a plurality of gate strips, each gate strip is a gate terminal of a transistor; forming a plurality of first contact vias connected to a part of the gate strips; forming a plurality of first metal strips above the plurality of gate strips; connecting one of the first metal strips to one of the first contact vias; forming a plurality of second metal strips above the plurality of first metal strips, wherein the plurality of second metal strips are co-planar, each second metal strip and one of the first metal strips are crisscrossed from top view; a length between two adjacent gate strips is twice as a length between two adjacent second metal strips, and a length of said one of the first metal strips is smaller than two and a half times as the length between two adjacent gate strips.