Gate Metal Removal via Dielectric Spacer Buffer
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Solution Overview
Problem
Current methods for removing gate metal from field-effect transistors during the replacement metal gate process face challenges such as undercutting and edge placement errors, particularly when differentiating between n-type and p-type transistors, and require multiple etch processes for various technology platforms.
Innovation Solution
A method involving the deposition of a dielectric spacer layer and a patterned buffer layer, followed by selective etching to remove gate metal from one region while protecting it in another, using a combination of dry and wet etching techniques to minimize undercutting and enable a single process for multiple technology platforms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple etch processes are used to remove gate metal from different transistor types, then manufacturing precision is improved, but device complexity and process time increase
Solution Approach 1:
The gate metal removal process is segmented into two distinct etch processes: a first etch process that removes gate metal from both n-type and p-type transistors, and a second etch process that selectively removes gate metal only from p-type transistors. This segmentation allows each etch process to be optimized for its specific function, improving overall manufacturing precision while maintaining manageable process complexity through clear process separation.
Solution Approach 2:
The patent applies local quality by using a spacer layer with different etch selectivity characteristics in different regions of the device. The spacer layer provides selective protection during the etch processes, allowing the first etch to access gate metal in both transistor types while the second etch selectively accesses only p-type transistor gate metal. This local differentiation in etch accessibility achieves high precision gate metal removal without requiring complex process sequencing.
2Device complexity
If a single etch process is used to remove gate metal from all transistors, then device complexity is reduced, but manufacturing precision deteriorates due to inability to differentiate between n-type and p-type transistors
Solution Approach 1:
The gate metal removal is segmented into two etch processes with distinct functions. The first etch process uses the spacer layer as a protective mask to remove gate metal from both n-type and p-type transistors. The second etch process selectively removes gate metal from p-type transistors by exploiting the spacer layer's selective protection of n-type transistors. This segmentation enables precise differentiation between transistor types while keeping the overall process structure simple and manageable.
Solution Approach 2:
The spacer layer is formed as a preliminary structure before the etch processes begin. This preliminary action creates a protective mask that dictates the selectivity of subsequent etch processes. By pre-establishing the spacer layer with its specific etch selectivity properties, the patent enables precise gate metal removal from different transistor types without requiring complex real-time process control, thus maintaining low device complexity while achieving high manufacturing precision.
3Manufacturing precision
If the wet etch duration is extended to ensure complete gate metal removal, then manufacturing precision is improved, but undercutting at the n/p boundary increases
Solution Approach 1:
The gate metal removal is divided into two sequential etch processes rather than one extended etch. The first etch process is optimized to remove gate metal from both transistor types with controlled duration to minimize undercutting. The second etch process completes the gate metal removal from p-type transistors with additional selectivity. This segmentation allows each etch to be shorter and more controlled, achieving complete gate metal removal while reducing cumulative undercutting at the n/p boundary compared to a single long etch process.
Solution Approach 2:
The spacer layer is formed as a preliminary protective structure before etching begins. This preliminary action creates a controlled etch front that prevents excessive undercutting during the first etch process. The spacer layer's presence during the first etch ensures that gate metal removal is confined to areas where the spacer provides protection, reducing lateral etching and undercutting at the n/p boundary while still achieving complete gate metal removal through the coordinated two-etch approach.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces undercutting at the n/p boundary, allows for the use of a long wet etch, and enables a single process for both high-performance and general-purpose transistor designs, improving accuracy and efficiency in gate metal removal.
Implementation Method 1
A dielectric spacer layer is deposited over the monolithic structure
Implementation Method 2
the monolithic structure is subjected to a wet second etch, thereby removing the layer of gate metal from the second field-effect transistor structure
Data Source
AI summary
Gate metal is removed from a region containing transistors such as nanosheet transistors or vertical transport field-effect transistors using techniques that control the undercutting of gate metal in an adjoining region. A dielectric spacer layer is deposited on the transistors. A first etch causes the removal of gate metal over the boundary between the regions with limited undercutting of gate metal beneath the dielectric spacer layer. A subsequent etch removes the gate metal from the transistors in one region while the gate metal in the adjoining region is protected by a buffer layer. Gate dielectric material may also be removed over the boundary between regions.