Half-Bridge Gate Driver Current Mirroring for Dead-Time Reduction

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Solution Overview

Problem

Existing power converters face significant challenges in controlling dead-time transitions due to the risk of shoot-through currents and high losses associated with reverse conduction modes, particularly in wide band gap devices like SiC and GaN, which are exacerbated by complex and costly solutions involving additional sensors and controllers.

Innovation Solution

A gate driver circuit using current mirroring circuits to sense and mirror gate current signals across insulation barriers, allowing advanced control of switching transitions to reduce dead-time without shoot-through, using pre-driver circuits and gate buffers for insulation and signal conditioning.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If dead-time is extended to prevent shoot-through currents, then device reliability is improved, but power losses increase due to reverse conduction

Engineering Contradiction:
Improvedevice reliabilityVSAvoidpower losses
Core Design Contradiction:
ReliabilityVSLoss of energy

Solution Approach 1:

The gate current mirror circuit performs preliminary action by detecting the gate current of the turning-off device and triggering the turn-on of the opposite device before the dead-time ends. This advance triggering reduces the reverse conduction time of the body diode, thereby reducing power losses during the dead-time period while maintaining reliable operation.

Inventive Principle:
Principle #10Preliminary action

2Loss of energy

If dead-time is reduced to minimize reverse conduction losses, then power efficiency is improved, but the risk of shoot-through currents increases

Engineering Contradiction:
Improvereverse conduction lossesVSAvoidshoot-through risk
Core Design Contradiction:
Loss of energyVSReliability

Solution Approach 1:

The gate current mirror circuit implements feedback by continuously monitoring the gate current of the turning-off device and using this information to control the turn-on timing of the opposite device. The mirror circuit provides real-time feedback on the switching state, enabling precise control that reduces dead-time while preventing shoot-through currents through intelligent triggering based on actual device state.

Inventive Principle:
Principle #23Feedback

3Manufacturing precision

If complex control circuits with sensors and microcontrollers are used to optimize dead-time, then switching precision is improved, but device complexity and cost increase

Engineering Contradiction:
Improveswitching precisionVSAvoidcircuit complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The gate current mirror circuit uses the copying principle by creating a mirrored version of the gate current signal through transistor mirroring. This copied current signal is then used to trigger the opposite device, eliminating the need for complex voltage sensing circuits, microcontrollers, and associated control logic while achieving precise dead-time control through the inherent current mirroring action.

Inventive Principle:
Principle #26Copying

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Effectively reduces dead-time transitions, minimizing reverse conduction losses and shoot-through risks, while maintaining fast switching speeds and reducing system complexity and cost.

Implementation Method 1

A gate driver circuit using current mirroring circuits to sense and mirror gate current signals across insulation barriers

Methodology Applied
Scientific EffectCurrent mirror effect:

Data Source

PatentEP4369603B1Dead-time reduction using gate current mirror in a power converter
Publication Date: 2025.11.26 MITSUBISHI ELECTRIC R&D CENTRE EUROPE BV
  • EP4369603B1 patent drawingFigure 1~2
  • EP4369603B1 patent drawingFigure 3A
  • EP4369603B1 patent drawingFigure 3B

AI summary

Gate driver circuit, for a half bridge of a converter (100) where a first switching device (SH), having a first gate, and a second switching device (SL), having a second gate, are controlled independently and in a complementary way respectively through a first gate driver buffer (1a) and a second gate driver buffer (1b), and a controller (60) providing gate pull up and gate pull down pulse signals to the first and second gate drivers buffers, comprising a first gate current mirroring circuit (2a) on a sink branch of said first gate driver buffer (1a) and a second gate current mirroring circuit (2b) on a sink branch of said second gate driver buffer (1b) to provide, in advance from said pulse signals (GP1, .GP2) issued from the controller (60), a first early gate pullup command signal (EC1) issuing from the first gate current mirroring circuit (2a), for the second gate driver buffer (1b) under a turning off of said first switching device (SH) and a second early gate pullup command signal (EC2) issuing from the second gate current mirroring circuit (2b), for the first gate driver buffer (1a) from a turning off of said second switching device (SL), in advance from gate pull up pulse signals (GP1, GP2) issued from the controller (60).