Gate Modulation Circuit for Liquid Crystal Display Scan Line Signal Control
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Solution Overview
Problem
Conventional liquid crystal displays suffer from image mura issues such as flickers and residues due to inconsistent level shifts in drain voltage, which are caused by the rapid falling edge of the scanning signal, requiring modifications to timing integrated circuits and scan line drivers.
Innovation Solution
A gate signal modulation circuit is introduced, comprising a first capacitor, a constant current circuit, a voltage generation circuit, and a discharging circuit to generate a triangle wave voltage and modulate the falling edge of the scan line timing signal, allowing for a ramp waveform without modifying existing timing integrated circuits or scan line drivers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the scanning signal falls rapidly to enable fast switching, then the switching speed is improved, but the level shift inconsistency causes image mura
Solution Approach 1:
The patent applies dynamics by making the falling edge of the scanning signal time-dependent. Specifically, the falling edge duration is dynamically adjusted based on the pixel position along the scan line - pixels near the input end receive a longer falling edge duration than pixels near the output end. This dynamic adjustment compensates for the delay effect in the scan line, ensuring consistent level shifts across all pixels while maintaining fast switching overall.
Solution Approach 2:
The patent changes the parameter of falling edge duration as a function of position along the scan line. By varying this temporal parameter based on spatial position, the invention achieves consistent drain voltage level shifts across different pixel locations, thereby eliminating image mura while preserving the benefits of rapid switching.
2Manufacturing precision
If the falling edge of the scanning signal is extended to reduce level shift inconsistency, then the image quality is improved, but the switching speed decreases
Solution Approach 1:
The patent applies local quality by providing different falling edge durations to different pixels along the scan line based on their specific positions. Pixels near the input end receive longer falling edges, while pixels near the output end receive shorter falling edges. This localized differentiation ensures each pixel receives the optimal falling edge duration for its position, achieving uniform image quality without requiring a universally extended falling edge that would slow down overall switching.
3Manufacturing precision
If the timing integrated circuit and scan line driver are modified to implement ramp waveform, then the image mura is reduced, but the device complexity increases
Solution Approach 1:
The patent introduces a falling edge control circuit as an intermediary component between the scan line driver and the scan line. This intermediary circuit generates position-dependent falling edge durations and applies them to the scanning signal, thereby achieving image mura reduction without requiring modifications to the existing timing integrated circuit or scan line driver structures. The intermediary approach adds minimal complexity while solving the image quality problem.
Data Source
AI summary
A gate modulation circuit is provided. A comparator compares a triangular wave voltage of a capacitor with a second reference voltage. If the triangular wave voltage of the capacitor exceeds the second reference voltage, a conduction path is turned off. A comparator controls desired discharge to a capacitor through a discharge resistor. Based on the discharge, power voltage (high level power voltage of the scanning driver) provided to the scanning driver is modulated, and outputted from the gate modulation circuit to the scanning driver as high level power voltage of the scanning driver.