Gate Modulation for Wide Bandgap Semiconductor Ringing Suppression

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Solution Overview

Problem

Wide band gap semiconductor devices experience high frequency ringing during switching, leading to electromagnetic interference and performance issues, which existing solutions like improved packaging and external passive components fail to adequately address, especially in high-power applications like hybrid and electric vehicles.

Innovation Solution

Implementing gate modulation techniques that create a period of operational overlap between semiconductor devices to reduce lumped stray capacitance and increase lumped loop resistance, utilizing inherent device characteristics without additional hardware, and allowing for adjustable control of ringing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Object-generated harmful factors

If external passive components (R/C snubber circuits) are added to minimize ringing, then ringing is reduced, but device complexity increases, packaging cost and size increase, and reliability decreases during high temperature operation

Engineering Contradiction:
ImproveringingVSAvoiddevice complexity
Core Design Contradiction:
Object-generated harmful factorsVSDevice complexity

Solution Approach 1:

The patent extracts the ringing suppression function from external passive components and relocates it to the gate drive circuitry. By manipulating the gate voltage to create an intermediate state, the system eliminates the need for external R/C snubber circuits while maintaining ringing suppression functionality.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The gate drive circuitry performs dual functions: it both switches the semiconductor device and suppresses ringing. The gate drive circuitry uses its own output capability to create an intermediate voltage state that suppresses ringing without requiring separate suppression components.

Inventive Principle:
Principle #25Self-service

2Object-generated harmful factors

If external passive components are added to minimize ringing, then ringing is reduced, but dv/dt and di/dt speeds decrease, which greatly increases switching loss

Engineering Contradiction:
ImproveringingVSAvoidswitching loss
Core Design Contradiction:
Object-generated harmful factorsVSLoss of energy

Solution Approach 1:

The patent removes the damping effect of external passive components and replaces it with an active gate voltage manipulation strategy. This extraction allows the system to maintain fast dv/dt and di/dt switching speeds while still suppressing ringing through controlled intermediate voltage states.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent dynamically changes the gate voltage parameter to an intermediate value during switching transitions. This parameter change creates a controlled state that suppresses ringing without the need for external resistive damping, thereby maintaining fast switching speeds and low switching losses.

Inventive Principle:
Principle #35Parameter changes

3Object-generated harmful factors

If packaging stray inductance is reduced to minimize ringing, then parasitic inductance is minimized, but packaging cost increases and the solution is difficult to achieve in high power applications

Engineering Contradiction:
ImproveringingVSAvoidease of manufacture
Core Design Contradiction:
Object-generated harmful factorsVSEase of manufacture

Solution Approach 1:

The patent extracts the ringing suppression function from packaging design modifications and relocates it to the gate drive control strategy. This allows standard packaging to be used without modification while achieving ringing suppression through electronic control of the gate voltage.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent changes the operational parameters of the gate drive circuitry to create an intermediate voltage state that suppresses ringing. This parameter-based solution avoids the need for costly and complex packaging modifications, making it easier to manufacture and implement in high power applications.

Inventive Principle:
Principle #35Parameter changes

4Object-generated harmful factors

If gate voltage is set to intermediate value above threshold voltage during switching overlap, then ringing is minimized by reducing lumped stray capacitance and increasing lumped loop resistance, but this requires precise gate drive control

Engineering Contradiction:
ImproveringingVSAvoidease of operation
Core Design Contradiction:
Object-generated harmful factorsVSEase of operation

Solution Approach 1:

The patent dynamically adjusts the gate voltage to an intermediate value during the switching overlap period. This dynamic control creates a temporary state that suppresses ringing by reducing stray capacitance effects and increasing loop resistance, then returns to normal switching operation after the overlap period.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent applies periodic gate voltage modulation during switching transitions. The gate drive circuitry periodically sets the voltage to an intermediate value during the overlap period, creating a controlled periodic action that suppresses ringing at critical moments while maintaining normal operation otherwise.

Inventive Principle:
Principle #19Periodic action

Data Source

PatentUS10193544B2Minimizing ringing in wide band gap semiconductor devices
Publication Date: 2019.01.29 FORD GLOBAL TECH LLC
  • US10193544B2 patent drawing
  • US10193544B2 patent drawing
  • US10193544B2 patent drawing

AI summary

Embodiments include a power conversion circuit comprising first and second semiconductor switches, and a drive circuit configured to create a period of operational overlap for the first and second switches by setting a gate voltage of the first switch to an intermediate value above a threshold voltage of the first switch, during turn-on and turn-off operations of the second switch. Embodiments also include a method of operating first and second semiconductor devices, comprising: reducing a gate voltage of the first device to an intermediate value above a threshold voltage while the second device is off; turning off the first device after the second device is on; increasing the gate voltage of the first device to the intermediate value while the second device is on; and fully turning on the first device after the second device is off.