Gate-on-array Driving Unit for Narrow Bezel Displays
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Solution Overview
Problem
Existing gate-on-array (GOA) driving circuits for low temperature poly-silicon display panels require numerous signal lines and transistors, making it difficult to achieve a narrow bezel width of less than 1 mm due to their complex structure.
Innovation Solution
A simplified GOA driving unit with only five transistors and one capacitor, utilizing a reduced number of signal lines and employing a phase-reversed clock signal to control the output of gate driving signals, allowing for a more compact circuit design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional GOA driving circuit with seven transistors and two storage capacitors is used, then the driving function is reliable, but the circuit area is too large to achieve a narrow bezel width of less than 1 mm
Solution Approach 1:
The patent extracts and removes redundant components from the conventional 7T2C GOA driving circuit. Specifically, it eliminates one storage capacitor and reconfigures the transistor network to use only five transistors while retaining the essential driving functionality. This extraction of unnecessary elements directly reduces the circuit area to enable narrow bezel designs.
Solution Approach 2:
The patent merges multiple functions into fewer components. The simplified circuit structure combines the functions of signal transmission, storage, and control into a more compact configuration using only five transistors and one capacitor, rather than the separate functions performed by seven transistors and two capacitors in the conventional design.
2Reliability
If seven transistors and two storage capacitors are used in the GOA driving circuit, then the driving capability is sufficient, but the number of signal lines and transistors makes it difficult to provide a display device with a narrow bezel
Solution Approach 1:
The patent extracts and removes redundant components from the conventional 7T2C GOA driving circuit. Specifically, it eliminates one storage capacitor and reconfigures the transistor network to use only five transistors while retaining the essential driving functionality. This extraction of unnecessary elements directly reduces the circuit area to enable narrow bezel designs.
Solution Approach 2:
The patent merges multiple functions into fewer components. The simplified circuit structure combines the functions of signal transmission, storage, and control into a more compact configuration using only five transistors and one capacitor, rather than the separate functions performed by seven transistors and two capacitors in the conventional design.
3Reliability
If more transistors and capacitors are used in the GOA driving circuit, then the driving stability is improved, but the production cost increases and the bezel width cannot be reduced below 1 mm
Solution Approach 1:
The patent extracts and removes redundant components from the conventional 7T2C GOA driving circuit. Specifically, it eliminates one storage capacitor and reconfigures the transistor network to use only five transistors while retaining the essential driving functionality. This extraction of unnecessary elements directly reduces the circuit area to enable narrow bezel designs.
Solution Approach 2:
The patent merges multiple functions into fewer components. The simplified circuit structure combines the functions of signal transmission, storage, and control into a more compact configuration using only five transistors and one capacitor, rather than the separate functions performed by seven transistors and two capacitors in the conventional design.
Data Source
AI summary
GOA driving unit includes an input end, a starting module, a control module, an output module and a gate driving signal output end. The starting module is configured to, within a starting time period, input a triggering signal from the input end into the control module under the control of a first clock signal. The control module is configured to, within an output time period, output a second clock signal to the output module. The output module is configured to output a first level to the gate driving signal output end within the starting time period, output the second clock signal to the gate driving signal output end within the output time period, and output the first level to the gate driving signal output end within a maintenance time period. The first clock signal is of a phase reverse to the second clock signal.