3D Memory Gate Connection Openings for Reliable Vertical Contacts
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Solution Overview
Problem
Integrated circuit devices face challenges in achieving high performance, small size, and low cost while maintaining electrical connection reliability, particularly in 3-dimensional nonvolatile memory devices where existing technologies struggle with effective integration and reliability.
Innovation Solution
The proposed integrated circuit device includes a substrate with a memory cell area and connection area, featuring a gate stack with gate electrodes arranged vertically, gate connection openings, and gate connection structures that cover inner and bottom surfaces of these openings, ensuring reliable electrical connections through the use of dummy structures and conformal coverage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If 3-dimensional nonvolatile memory devices are used to achieve high degrees of integration, then device density and capacity are improved, but electrical connection reliability deteriorates
Solution Approach 1:
The gate stack is segmented into multiple gate electrodes (first gate electrode, second gate electrode, third gate electrode) at different vertical levels, with corresponding gate connection openings formed at each level. This segmentation allows independent electrical connection to each gate electrode through separate contact structures, ensuring reliable electrical connection while maintaining high vertical integration density.
Solution Approach 2:
The patent transitions from planar 2D memory architecture to 3D vertical architecture by stacking multiple gate electrodes and memory cell strings in the vertical direction. Gate connection openings extend from the upper surface downward to reach each gate electrode, enabling electrical connection in the vertical dimension while achieving high device density without compromising connection reliability.
2Quantity of substance
If stepwise gate stack structures are used to achieve high integration, then device density is improved, but manufacturing complexity increases
Solution Approach 1:
A fill structure is formed in advance within the gate connection opening before the gate contact is deposited. This preliminary action simplifies subsequent manufacturing steps by providing a predefined structural foundation, eliminating the need for complex stepwise gating processes and reducing overall manufacturing complexity while maintaining high device density.
Solution Approach 2:
The gate stack structure is designed with uniform characteristics across different vertical levels, where each gate electrode is surrounded by insulating layers and connected through similarly structured gate connection openings. This homogeneity allows standardized manufacturing processes to be applied repeatedly, reducing manufacturing complexity despite the vertical integration.
3Reliability
If contact holes of varying heights are required to reach different gate electrodes, then electrical connection to multiple gate levels is achieved, but fabrication difficulty increases
Solution Approach 1:
The fill structure serves as an intermediary element within the gate connection opening, providing a uniform reference plane and structural support. This intermediary allows the gate contact to be formed at a single height level while still establishing electrical connection to gate electrodes at different vertical levels through the fill structure, thereby simplifying fabrication by eliminating the need to create contact holes of varying heights.
Data Source
AI summary
An integrated circuit device includes a substrate including a memory cell area and a connection area, a gate stack including a plurality of gate electrodes apart from each other in a vertical direction on the substrate, a plurality of gate connection openings arranged in the connection area to extend inward from an upper surface of the gate stack, one of the plurality of gate electrodes being exposed at a bottom surface of each of the plurality of gate connection openings, a plurality of gate connection structures respectively covering at least inner side surfaces of the plurality of gate connection openings, each of the plurality of gate connection structures being connected with the one gate electrode, and a plurality of gate contacts respectively connected to upper ends of the plurality of gate connection structures.