Test Key Structures for Decoupling Gate Overlap Capacitance
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Solution Overview
Problem
As integrated circuit dimensions shrink, parasitic capacitances become significant, making it difficult to accurately measure and decouple gate to source/drain and overlap capacitances from total gate capacitance, as conventional test methods fail to distinguish between these capacitances effectively.
Innovation Solution
A method using a first and second test key structure, where the first test key includes a gate, gate dielectric layer, spacer, doping region, contact, and metal layer, and the second test key lacks a doping region, allowing for the measurement and deduction of capacitances to isolate gate to source/drain and overlap capacitances from total capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional test methods are used to measure total gate capacitance, then measurement is simple, but gate to source/drain and overlap capacitances cannot be decoupled from contact and metal layer capacitances
Solution Approach 1:
The patent segments the total capacitance measurement into multiple separate measurements by dividing the gate into different regions (first gate region with doping region, second gate region without doping region). Each region is measured separately to isolate specific capacitance components (C1+C2, C3+C4), enabling precise decoupling of overlap capacitance from contact and metal layer capacitances.
Solution Approach 2:
The patent introduces an intermediary structure (doping region) that acts as a selector to include or exclude specific capacitance components in the measurement. By presence or absence of the doping region, the measurement can selectively capture either C1+C2 or C3+C4, serving as a mediator to separate the total capacitance into distinct measurable components.
2Productivity
If IC dimensions are shrunk to increase density, then productivity and cost efficiency improve, but parasitic capacitance effects become significant and reduce transistor performance
Solution Approach 1:
The patent replaces physical modification of the transistor structure with an electrical measurement methodology. Instead of changing the transistor design to reduce parasitic capacitance, the patent uses a specialized test key structure with selective doping regions to electrically measure and separate capacitance components, allowing accurate characterization without structural modifications.
Solution Approach 2:
The patent changes the measurement parameters by varying the gate structure configuration (presence/absence of doping region, different gate lengths) to selectively measure different capacitance components. By changing structural parameters in the test key, the measurement can isolate specific capacitance values that are relevant to transistor performance at scaled dimensions.
Data Source
AI summary
A method to extract gate to source/drain and overlap capacitances is disclosed. A first capacitance of a first test key having a reference structure and a second capacitance of a second test key having a novel structure are measured. The second test key may comprise at least a gate formed on an insulation structure, at least a contact formed on the insulation structure aside, and a metal layer formed on the contact. Another embodiment of the second test key may comprise at least a gate formed on the semiconductor substrate, a contact formed aside, and a metal layer formed on the contact. Further another embodiment uses a test key comprising at least an elongated gate and an elongated doping region aside, and only one or a few contacts are formed on an end portion of the elongated doping region.