Gate Oxide Integrity Detection Structure for Contamination Sensitivity
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Solution Overview
Problem
Existing methods for evaluating gate oxide integrity (GOI) in semiconductor devices are inadequate in detecting contamination, as they are not sensitive enough to detect low levels of contaminants and can be influenced by surrounding structures, leading to unreliable GOI testing and increased yield loss.
Innovation Solution
A detection structure is formed with a deep trench isolation oxide and a capacitor having a smaller n-type well surrounded by a p-type well, allowing for the collection of contaminants and sensitive parametric testing to determine gate oxide integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional GOI testing methods are used, then testing can be performed on standard devices, but the methods are not sensitive enough to detect low levels of contaminants
Solution Approach 1:
The device is segmented into distinct functional regions: a collection region (first doped region) with larger area for contaminant accumulation, and a testing region (second doped region) with smaller area for sensitive GOI measurement. This segmentation allows the testing structure to achieve high contamination detection sensitivity while maintaining manageable complexity by separating the collection and detection functions.
2Reliability
If large gate oxide area is used to increase probability of catching defects, then more defects can be detected, but contaminates are averaged out and never reach critical density level
Solution Approach 1:
The testing structure implements local quality by creating a concentrated contamination collection zone (first doped region) that funnels contaminants to a specific location, and a separate measurement zone (second doped region) where the gate oxide integrity is tested. This local differentiation ensures that contaminants are not averaged out but concentrated to reach critical density levels at the testing location, enabling precise contamination density measurement while maintaining reliable defect detection capability.
3Loss of time
If GOI testing is performed early in FEOL, then unnecessary processing time and resources are saved, but contamination detection accuracy is reduced due to insufficient contaminant accumulation
Solution Approach 1:
The structure performs preliminary contamination collection during normal device fabrication processes before GOI testing is conducted. The first doped region acts as a pre-positioned collection site that accumulates contaminants throughout the fabrication process, ensuring that by the time GOI testing occurs in FEOL, sufficient contaminant accumulation has already taken place. This preliminary action enables accurate contamination detection early in the process flow without requiring extended processing time.
4Reliability
If surrounding structures are present during GOI testing, then the testing reflects real device conditions, but the surrounding structures influence the testing results and reduce reliability
Solution Approach 1:
The testing structure extracts the essential GOI testing function from the complex surrounding device environment by creating a self-contained testing region (second doped region with gate oxide) that is electrically and physically isolated. This extracted testing zone can be influenced by surrounding structures during normal operation but maintains independent measurement capability, allowing accurate contamination detection that reflects real device conditions while minimizing interference from surrounding structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively quantifies contamination impact on GOI, providing timely feedback and reducing yield loss by quickly reaching critical contamination density for accurate breakdown voltage distribution analysis.
Implementation Method 1
contaminates 101 diffuse through substrate 105 and collect at the bottom side of the silicon substrate 102
Implementation Method 2
performing parametric testing on the capacitor over a plurality of breakdown voltages and determining the gate oxide integrity of the capacitor based on the parametric testing
Data Source
AI summary
A method of forming an integrated circuit on a substrate is described herein. The method includes forming a first doped region of a detection structure on the substrate, the first doped region comprises a first doped conductivity type. The method forming a capacitor of the detection structure, which includes forming a second doped region of a second conductivity type opposite the first doped conductivity type, the second doped region surrounded by the first doped region. The second doped well comprises a top surface area smaller than a top surface area of the first doped region. The method includes performing parametric testing on the capacitor over a plurality of breakdown voltages. The method includes determining the gate oxide integrity of the capacitor based on the parametric testing over the plurality of breakdown voltages.