Gate Oxide Fabrication for Non-Volatile Memory Retention
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Solution Overview
Problem
As technology scales to smaller dimensions and lower voltages, non-volatile memory devices face reduced charge retention time due to direct tunneling when gate oxides are scaled below 50 Angstroms, and additional heat from thickening gate oxides through thermal oxidation can cause dopant diffusion, affecting other device performance.
Innovation Solution
A method involving the formation of shallow trench isolation regions, selective filling with oxide, forming sacrificial oxide regions, and implant regions in a silicon wafer, followed by the creation of a gate oxide, which includes depositing and etching oxide and nitride layers, and selectively removing sacrificial oxides to achieve a thick gate oxide without excessive heat exposure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If gate oxide is scaled below 50 Angstroms to enable smaller device dimensions, then device scaling is achieved, but charge retention time is reduced below 10 years due to direct tunneling
Solution Approach 1:
The gate oxide structure is segmented into multiple layers: a thin first gate oxide layer (30-50 Angstroms) for device scaling and a thicker second gate oxide layer (100-200 Angstroms) for charge retention. This segmentation allows each layer to fulfill different functional requirements simultaneously.
Solution Approach 2:
The gate oxide structure uses a composite of two different oxide materials with different thicknesses and properties. The first oxide layer provides the necessary thinness for scaled devices while the second oxide layer provides the thickness needed for charge retention, creating a composite structure that achieves both goals.
2Duration of action of stationary object
If another gate oxide is added by thermal oxidation to increase charge retention time, then charge retention time is improved, but heat causes dopants in the semiconductor material to diffuse, affecting device performance
Solution Approach 1:
The first gate oxide layer is formed preliminarily before the second oxide layer. This preliminary action allows the thin oxide to be in place for device operation while the thicker second oxide is added subsequently to enhance charge retention without requiring high-temperature processing that would cause dopant diffusion.
Solution Approach 2:
The patent changes the formation parameters of the second oxide layer by using low-temperature oxidation or deposition methods instead of traditional high-temperature thermal oxidation. This parameter change allows oxide growth without causing dopant diffusion, thus maintaining device performance while improving charge retention.
3Length of moving object
If I/O devices are scaled down to 1.8V to match smaller dimensions, then device scaling is achieved, but floating gate NVM with standard 10 year retention is no longer possible
Solution Approach 1:
The patent applies local quality by creating different oxide thicknesses in different regions of the device. The first gate oxide layer provides thinness for scaled 1.8V operation while the second gate oxide layer provides enhanced thickness specifically for charge retention in the floating gate region, allowing both scaling and retention at lower voltages.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enhances charge retention time in non-volatile memory devices by reducing leakage currents and minimizing heat-induced dopant diffusion, ensuring reliable performance even at lower voltages.
Implementation Method 1
selectively removing the sacrificial oxide regions
Implementation Method 2
adding another gate oxide can be added by thermal oxidation to create thicker gate oxide
Data Source
AI summary
An example of a method of fabricating a gate oxide of a floating gate transistor includes forming a plurality of shallow trench isolation (STI) regions in a silicon wafer. The method also includes selectively filling the STI regions with oxide. Further, the method includes forming sacrificial oxide regions on the silicon wafer. Furthermore, the method includes forming implant regions in the silicon wafer. In addition, the method includes selectively removing the sacrificial oxide regions. The method further includes forming the gate oxide.