High-Voltage Transistor Gate Oxide Layout for Lower GIDL
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Solution Overview
Problem
High voltage transistors face issues with gate-induced drain leakage (GIDL) due to reduced spacing between the gate structure and source/drain regions, leading to increased standby power consumption and heat dissipation, which reduces their operational lifespan.
Innovation Solution
The gate oxide layer extends laterally outward from under the gate structure, serving as a self-aligned structure to form source/drain regions at a greater spacing, thereby reducing depletion region encroachment and minimizing GIDL.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the spacing between gate structure and source/drain regions is reduced, then device integration density is improved, but gate-induced drain leakage increases
Solution Approach 1:
A gate oxide layer extension is introduced as an intermediary structure between the gate structure and source/drain regions. This extension creates a physical barrier that prevents depletion region encroachment and eliminates GIDL, while allowing the source/drain regions to be positioned closer to the gate for higher integration density.
Solution Approach 2:
The gate oxide layer is extended laterally outward from under the gate structure in a horizontal direction, creating an additional spatial dimension for controlling the interaction between gate and source/drain regions. This lateral extension provides a protective barrier without increasing vertical device height.
2Productivity
If the spacing between gate structure and source/drain regions is reduced, then device integration density is improved, but standby power consumption increases
Solution Approach 1:
The gate oxide layer extension serves as a protective intermediary that blocks the depletion region from reaching the source/drain regions during standby conditions. This eliminates the leakage current path that would otherwise consume standby power, while maintaining compact spacing for high density.
3Productivity
If the spacing between gate structure and source/drain regions is reduced, then device integration density is improved, but heat dissipation increases
Solution Approach 1:
The gate oxide layer extension acts as a thermal and electrical barrier that prevents excessive heat generation from GIDL effects. By blocking depletion region encroachment, it reduces unwanted current flow and associated heat dissipation, while allowing close spacing for compact device layout.
Data Source
AI summary
A high voltage transistor may include a plurality of source/drain regions, a gate structure, and a gate oxide layer that enables the gate structure to selectively control a channel region between the source/drain regions. The gate oxide layer may extend laterally outward toward one or more of the plurality of source/drain regions such that at least a portion of the gate oxide layer is not under the gate structure. The gate oxide layer extending laterally outward from under the gate structure enables the gate oxide layer to be used as a self-aligned structure for forming the source/drain regions of the high voltage transistor. In particular, the gate oxide layer extending laterally outward from under the gate structure enables the gate oxide layer to be used to form the source/drain regions at a greater spacing from the gate structure without the use of additional implant masks when forming the source/drain regions.