Gate Oxide Thickness Control for Mixed-Power FETs
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Solution Overview
Problem
The semiconductor industry faces challenges in scaling down semiconductor devices while maintaining low power consumption and reducing manufacturing costs and time, as existing methods are inefficient and costly in forming FETs with varying power levels on the same substrate.
Innovation Solution
The proposed solution involves forming FETs with different gate oxide structures by using a high-k gate dielectric layer interposed between interfacial oxide layers of varying thicknesses, achieved through controlled oxidation processes and capping layers with distinct oxygen diffusivities, allowing for different power consumption levels without increasing gate resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional gate oxide structures are used in scaled-down semiconductor devices, then manufacturing processes become more complex and costly, but power consumption increases and performance decreases
Solution Approach 1:
The gate oxide structure is segmented into multiple distinct layers: a first oxide layer with higher oxygen diffusivity and a second oxide layer with lower oxygen diffusivity. This segmentation allows each layer to perform specific functions - the first layer provides oxygen supply during annealing while the second layer controls oxygen diffusion to prevent excessive oxidation, thereby reducing power consumption without increasing manufacturing complexity
Solution Approach 2:
The patent changes the oxygen diffusivity parameter by selecting different materials for the first and second oxide layers. The first oxide layer uses materials with higher oxygen diffusivity (such as silicon oxide) while the second oxide layer uses materials with lower oxygen diffusivity (such as silicon nitride or silicon oxynitride). This parameter change enables precise control over oxygen diffusion during thermal annealing, achieving low power consumption devices through controlled oxidation
2Productivity
If device dimensions are scaled down to increase storage capacity and processing speed, then manufacturing complexity increases, but maintaining low power consumption becomes difficult
Solution Approach 1:
The patent applies local quality by creating non-uniform oxygen distribution through the layered oxide structure. The first oxide layer (higher oxygen diffusivity) is positioned where oxygen supply is needed during annealing, while the second oxide layer (lower oxygen diffusivity) is positioned to control and limit oxygen diffusion into the channel region. This local differentiation of oxygen diffusivity properties enables precise control over oxidation processes in scaled-down devices, achieving high processing speed with low power consumption
3Use of energy by moving object
If thicker oxide layers are used to reduce power consumption, then gate resistance increases, but if thinner oxide layers are used, then power consumption increases
Solution Approach 1:
The patent uses composite oxide structures combining materials with different oxygen diffusivity characteristics. The first oxide layer (higher oxygen diffusivity) and second oxide layer (lower oxygen diffusivity) work together as a composite system during thermal annealing. The first layer facilitates oxygen supply while the second layer acts as a diffusion barrier, enabling the formation of optimal oxide thickness that reduces power consumption without increasing gate resistance, as the composite structure controls oxidation more effectively than single-layer structures
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in cost-effective and time-efficient manufacturing of FETs with low power consumption, achieving a 20-30% cost reduction and 15-20% time savings while maintaining smaller dimensions without increased gate resistance.
Implementation Method 1
forming first and second oxide layers with first and second thicknesses, respectively... achieved through controlled oxidation processes and capping layers with distinct oxygen diffusivities
Implementation Method 2
capping layers with distinct oxygen diffusivities, allowing for different power consumption levels
Data Source
AI summary
A semiconductor device with different gate structure configurations and a method of fabricating the same are disclosed. The method includes forming first and second nanostructured channel regions on first and second fin structures, forming first and second oxide layers with first and second thicknesses, forming a dielectric layer with first and second layer portions on the first and second oxide layers, forming first and second capping layers with first and second oxygen diffusivities on the first and second layer portions, growing the first and second oxide layers to have third and fourth thicknesses, and forming a gate metal fill layer over the dielectric layer. The first and second thicknesses are substantially equal to each other and the first and second oxide layers surround the first and second nanostructured channel regions. The second oxygen diffusivity is higher than the first oxygen diffusivity. The fourth thickness is greater than the third thickness.