Controllable Gate Oxide Formation via Nitridation and Thermal Oxidation
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Solution Overview
Problem
Conventional techniques for forming gate dielectric layers in integrated circuits struggle to achieve ultra-thin thicknesses and controlled electric properties, often requiring expensive new machinery and being unable to produce gate oxide layers thinner than 20 angstroms.
Innovation Solution
A method involving a semiconductor substrate with defined source, drain, and gate regions, where a first layer of silicon nitride or oxynitride is formed through nitridation, followed by a controlled oxidation process in a conventional furnace to create a second layer of silicon oxide with a thickness less than 20 angstroms, and optionally a second nitridation step to incorporate nitrogen, allowing for a controllable and ultra-thin gate dielectric layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional oxidation techniques are used to form gate dielectric, then the process is simple and uses existing equipment, but the gate oxide thickness cannot be reduced below 20 angstroms
Solution Approach 1:
The oxidation process is divided into multiple sequential stages: initial oxidation to form a first oxide layer, nitridation to form a nitride layer, and final oxidation to form the ultra-thin gate oxide. This segmentation allows precise control of each layer's thickness and properties, enabling gate oxide thickness below 20 angstroms while using conventional equipment.
Solution Approach 2:
A nitride layer is formed as an intermediate layer before the final oxidation step. This preliminary action modifies the substrate surface properties and controls the oxidation rate, enabling precise thickness control of the final gate oxide layer at ultra-thin dimensions.
2Manufacturing precision
If new machinery is used to achieve ultra-thin gate dielectric, then gate oxide thickness below 20 angstroms can be achieved, but the manufacturing cost increases
Solution Approach 1:
The method uses conventional furnace oxidation equipment that already exists in semiconductor manufacturing facilities. The process leverages the self-organizing nature of thermal oxidation to automatically form uniform ultra-thin oxide layers without requiring specialized deposition equipment, thereby avoiding additional capital investment.
Solution Approach 2:
The oxidation process parameters (temperature, time, atmosphere composition) are precisely controlled and modified across different stages to achieve ultra-thin gate oxide. By changing parameters rather than changing equipment, the method achieves advanced thickness control using existing machinery.
3Productivity
If gate dielectric thickness is reduced to improve device density, then circuit density increases, but the electric properties and reliability of the gate dielectric deteriorate
Solution Approach 1:
The gate dielectric structure comprises a composite of silicon oxide layers and silicon nitride layers. The nitride layer provides mechanical support and controls stress, while the oxide layers provide the required electrical insulation. This composite structure maintains excellent electric properties even at ultra-thin total thicknesses, enabling high circuit density without sacrificing reliability.
Solution Approach 2:
Different layers in the gate dielectric stack have different local properties optimized for specific functions: the nitride layer provides structural stability and stress control, while the oxide layers provide electrical insulation. This local optimization of material properties throughout the stack maintains overall device reliability at reduced thickness.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of thinner, more controllable gate dielectric layers with superior electric properties, utilizing conventional technology and equipment, thereby reducing costs and improving device performance.
Implementation Method 1
forming a first layer overlaying the gate region. The first layer includes silicon nitride and/or silicon oxynitride material
Implementation Method 2
form a second layer by oxidizing the semiconductor substrate overlaid with the first layer at a predetermined temperature range for a period of time. The second layer includes at least silicon oxide material
Data Source
AI summary
Method and system for forming gate structure with controllable oxide. The method includes a step for providing a semiconductor substrate and defining a source region and a drain region within the semiconductor substrate. Furthermore, the method includes a step for defining a gate region positioned between the source region and the drain region. Moreover, the method provides a step for forming a first layer overlaying the gate region. The first layer includes silicon nitride and/or silicon oxynitride material. Also, the method includes a step for forming a second layer by subjecting the semiconductor substrate to at least oxygen at a predetermined temperature range for a period of time. The second layer has a thickness less than 20 Angstroms.