Fully Oxidized Gate Oxide Formation for Scalable ROX Integration
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Solution Overview
Problem
Current reduced surface field oxide (ROX) processes in semiconductor manufacturing are not optimized for device scalability, limiting the electrical performance and reliability due to field oxide limitations in local oxidation of silicon (LOCOS) techniques.
Innovation Solution
A method for manufacturing a semiconductor device involving the formation of a fully oxidized gate oxide layer using a rapid thermal oxidation process, which includes forming a ROX layer, patterning, and fully oxidizing a silicon oxynitride layer to integrate with an input/output oxide layer, avoiding surface damage from wet etching processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If LOCOS technique is used to form ROX, then reduced surface field and improved electrical SOA are achieved, but device scalability is limited by field oxides
Solution Approach 1:
The patent changes the oxidation parameters by using rapid thermal oxidation (RTX) process with specific temperature ranges (700-900°C) and time durations (5-30 minutes) to form ROX layer with controlled thickness (50-200 nm). This parameter optimization enables better scalability while maintaining the electrical performance benefits of ROX structure
Solution Approach 2:
The patent replaces the conventional LOCOS field oxide formation mechanism with a controlled rapid thermal oxidation process that uses thermal diffusion rather than lateral oxide growth. This substitution eliminates the scalability limitations of LOCOS field oxides while preserving the ROX functionality for reducing surface field and improving safe operating area
2Ease of manufacture
If conventional oxidation process is used, then process simplicity is maintained, but ROX layer optimization for device performance is not achieved
Solution Approach 1:
The patent optimizes oxidation parameters including temperature (700-900°C), time (5-30 minutes), and atmosphere control to achieve precise ROX layer thickness (50-200 nm). These parameter changes enhance electrical performance while maintaining a relatively simple single-step oxidation process
Solution Approach 2:
The patent employs rapid thermal oxidation with controlled heating and cooling cycles. The periodic thermal action allows precise control of oxidation kinetics, enabling optimal ROX formation without requiring complex multi-step processes, thus balancing simplicity with performance
3Ease of manufacture
If wet etching process is used for patterning, then manufacturing ease is improved, but surface damage is introduced
Solution Approach 1:
The patent replaces wet chemical etching with a dry oxidation-based patterning approach. By using rapid thermal oxidation to selectively grow oxide layers that serve as masks, the process eliminates contact with corrosive wet chemicals, thereby preventing surface damage while maintaining patterning capability
Solution Approach 2:
The patent uses thermally grown oxide layers as intermediary masking elements instead of direct wet etching. The oxide mask serves as an intermediate structure that enables patterning without introducing surface damage from wet chemicals, and can be selectively removed later using standard processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances device scalability and electrical performance by optimizing the ROX layer integration, improving the breakdown voltage and reducing hot-carrier injection while maintaining a reduced surface field, thus achieving a better trade-off and safe operating area.
Implementation Method 1
fully oxidizing the patterned silicon oxynitride layer to form a fully oxidized gate oxide layer
Data Source
AI summary
A method for making a semiconductor device includes forming a ROX layer on a substrate and a patterned silicon oxynitride layer on the patterned ROX layer; conformally forming a dielectric oxide layer to cover the substrate, the patterned silicon oxynitride layer, and the patterned ROX layer; and fully oxidizing the patterned silicon oxynitride layer to form a fully oxidized gate oxide layer on the substrate.