Gate Oxide Layer Thickness Control via Sequential Wet Etching
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Solution Overview
Problem
The existing manufacturing processes for integrated circuit gate oxide layers face challenges in achieving multiple thicknesses simultaneously, leading to issues such as roughness, unevenness, and surface damage, particularly when high and low voltage devices share the same chip, which affects device efficiency and quality.
Innovation Solution
A method involving sequential wet etching processes with varying etching speeds is used to form gate oxide layers of different thicknesses, utilizing buffered oxide etchant and diluted hydrofluoric acid to remove and form layers, avoiding over-etching and substrate damage, and incorporating thermal oxidation or CVD processes for layer formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a single gate oxide layer thickness is used for all device regions, then the manufacturing process is simple, but high voltage devices cannot withstand the high voltage operation environment
Solution Approach 1:
The patent applies local quality by forming different gate oxide layer thicknesses in different device regions. Thick gate oxide layers are formed in high voltage device regions to withstand high voltage stress, while thin gate oxide layers are formed in low voltage device regions to maintain device performance. This is achieved through selective etching processes that remove oxide layers from specific regions, allowing each region to have optimized oxide thickness for its voltage requirements.
2Adaptability or versatility
If gate oxide layers with greatly different thicknesses are manufactured, then different voltage device requirements are met, but roughness and unevenness occur in the layers
Solution Approach 1:
The patent segments the gate oxide layer formation process into multiple stages. First, a thick gate oxide layer is formed across the entire substrate. Then, selective etching is performed to remove portions of the oxide layer from low voltage regions, creating the thickness variation needed for different voltage devices. This segmented approach prevents the roughness and unevenness that would result from attempting to form different thicknesses in a single step.
Solution Approach 2:
The patent applies preliminary action by first forming a uniform thick gate oxide layer across all device regions before performing selective etching. This preliminary formation ensures that the base oxide layer is uniform and free of defects, and subsequent etching only removes material rather than attempting to build different thicknesses from scratch, thereby maintaining layer quality and uniformity.
3Manufacturing precision
If conventional etching processes are used to remove gate oxide layers, then thickness variation is achieved, but over-etching and substrate damage occur
Solution Approach 1:
The patent changes the etching parameters by using a two-step etching process with different etchants. The first etching step uses a buffered oxide etch (BOE) with controlled concentration to remove the majority of the oxide layer. The second etching step uses a different etchant with adjusted parameters to complete the removal without damaging the substrate. This parameter optimization prevents over-etching and substrate surface damage while achieving the required thickness variation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures the formation of high-quality gate oxide layers with precise thicknesses, preventing roughness and surface damage, reducing production costs by eliminating the need for dry etching and photomasks, and avoiding the kink effect and gate oxide layer thinning.
Implementation Method 1
a first wet etching process is performed to remove a portion of the first gate oxide layer in the second device region
Implementation Method 2
The buffered oxide etchant is a solution of HF/NH4F in a ratio of 20:1 mixed with water
Implementation Method 3
The method of forming the third gate oxide layer is, for example, a thermal oxidation process
Implementation Method 4
a chemical vapor deposition (CVD) process or other suitable methods
Data Source
AI summary
A method of manufacturing gate oxide layers with different thicknesses is disclosed. The method includes that a substrate is provided first. The substrate has a high voltage device region and a low voltage device region. Then, a high voltage gate oxide layer is formed on the substrate. Afterwards, a first wet etching process is performed to remove a portion of the high voltage gate oxide layer in the low voltage device region. Then, a second wet etching process is performed to remove the remaining high voltage gate oxide layer in the low voltage device region. The etching rate of the second wet etching process is smaller than that of the first wet etching process. Next, a low voltage gate oxide layer is formed on the substrate in the low voltage device region.