Gate Oxide Thickness and Quality in Non-Volatile Memory Cells
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Solution Overview
Problem
Conventional non-volatile memory (NVM) cells face challenges in achieving thicker, higher quality gate oxides due to size reduction in CMOS processes, with dual gate oxide processes being limited and nitrogen implantation methods resulting in lower quality gate oxides with higher leakage currents.
Innovation Solution
A manufacturing process involving multiple implantation steps, such as deep N-well, HiNWell, HiPWell, P-well, and N-well implantations, followed by a rapid thermal process anneal, to enhance oxidation rates and quality of the front-end gate oxide, resulting in a thicker and more reliable gate oxide layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If nitrogen implantation is used to grow thicker gate oxide in a single oxidation step, then gate oxide thickness is increased, but gate oxide quality deteriorates with higher leakage current
Solution Approach 1:
The patent divides the gate oxide formation into multiple separate oxidation steps rather than attempting to grow the full thickness in a single step. This segmentation allows each oxidation step to produce higher quality oxide while accumulating to the desired total thickness, resolving the contradiction between thickness and quality.
Solution Approach 2:
The patent performs preliminary oxidation steps to build up the gate oxide thickness before final processing. By preparing the oxide layer in advance through multiple controlled oxidation steps, the method achieves both sufficient thickness and high quality without relying on nitrogen implantation.
2Reliability
If dual gate oxide process is used to form thicker gate oxide, then gate oxide quality is improved, but device complexity increases
Solution Approach 1:
The patent uses a single oxidation process that serves multiple functions: it grows the gate oxide to the desired thickness and ensures high quality simultaneously. This multi-functional approach eliminates the need for separate dual gate oxide processes, reducing manufacturing complexity while maintaining oxide quality.
Solution Approach 2:
The patent controls oxidation parameters (temperature, time, atmosphere) to optimize both oxide thickness and quality within a single process framework. By adjusting these parameters, the method achieves the results of a dual gate oxide process without the added complexity.
3Productivity
If size reduction of NVM cells is implemented in CMOS processes, then productivity is improved, but gate oxide thickness decreases
Solution Approach 1:
The patent addresses the thickness limitation in miniaturized devices by changing the temporal dimension of oxide growth - using multiple oxidation steps over time rather than relying on spatial constraints. This allows sufficient oxide thickness to be achieved even in reduced-size NVM cells, maintaining both high density and adequate oxide thickness.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of a thicker, higher quality gate oxide layer with reduced defects, improving NVM retention and reducing leakage currents, thus enhancing the overall performance of NVM cells.
Implementation Method 1
a rapid thermal process anneal, to enhance oxidation rates
Implementation Method 2
enhance oxidation rates and quality of the front-end gate oxide
Data Source
AI summary
A non-volatile memory cell includes a program transistor and a control capacitor. A portion of a substrate associated with the program transistor is exposed to multiple implantations (such as DNW, HiNWell, HiPWell, and P-well implantations). Similarly, a portion of the substrate associated with the control capacitor is exposed to multiple implantations (such as DNW, HiNWell, HiPWell, P-well, and N-well implantations). These portions of the substrate may have faster oxidation rates than other portions of the substrate, allowing a thicker front-end gate oxide to be formed over these portions of the substrate. In addition, a rapid thermal process anneal can be performed, which may reduce defects in the front-end gate oxide and increase its quality without having much impact on the oxide over the other portions of the substrate.