Gate Oxide Integrity via Buffered Wet Cleaning
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional semiconductor manufacturing processes face challenges in maintaining precise gate oxide thicknesses due to the formation of chemical oxides during cleaning operations, which compromises the integrity and thickness of gate oxides in the 10-20 angstrom range, especially when forming multiple gate oxides on the same substrate.
Innovation Solution
A wet cleaning sequence involving a series of treatments: HF, pure H2SO4, H2O2, DI water, and HCl is used to suppress oxide growth, ensuring the substrate is free of chemical oxides, thereby maintaining gate oxide integrity and allowing for accurate formation of multiple gate oxides with varying thicknesses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional wet cleaning operations (RCA clean, SPM solution) are used to clean the substrate after etching, then the substrate is cleaned effectively, but chemical oxide forms on the silicon surface compromising gate oxide integrity and thickness precision
Solution Approach 1:
The patent changes the chemical parameters of the cleaning solution by using a buffered oxide etch (BOE) with specific buffering agents and controlled pH, replacing conventional RCA or SPM solutions. This parameter change allows effective cleaning while suppressing chemical oxide formation, thus maintaining both gate oxide integrity and thickness precision
Solution Approach 2:
The patent introduces a buffered oxide etch solution as an intermediary between the etching process and oxide formation. The BOE acts as a mediator that removes etching residues and photoresist without causing the silicon surface to form chemical oxide, thereby protecting the gate oxide integrity while enabling precise thickness control
2Adaptability or versatility
If multiple gate oxides of various thicknesses are formed on the same substrate, then device functionality is improved, but the risk of chemical oxide formation during cleaning increases
Solution Approach 1:
The patent uses buffered oxide etch with controlled buffering capacity and pH to create a cleaning environment that suppresses chemical oxide formation. This allows multiple gate oxide regions with different thicknesses to be processed without contamination from unwanted oxide growth, maintaining reliability across all device regions
Solution Approach 2:
The patent performs cleaning with buffered oxide etch immediately after etching and before any oxide formation steps. This preliminary cleaning action removes all residues that could catalyze chemical oxide formation during subsequent processing, ensuring that multiple gate oxides form on clean surfaces with precise thickness control
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This cleaning sequence effectively prevents the growth of chemical oxides, maintaining the integrity of gate oxides and enabling the precise formation of multiple gate oxides with targeted thicknesses in the 10-20 angstrom range, reducing particle counts and watermark defects.
Implementation Method 1
first treating with a solution of HF
Implementation Method 2
treating with a solution of H2O2
Data Source
AI summary
A cleaning sequence usable in semiconductor manufacturing efficiently cleans semiconductor substrates while preventing chemical oxide formation thereon. The sequence includes the sequence of: 1) treating with an HF solution; 2) treating with pure H2SO4; 3) treating with an H2O2 solution; 4) a DI water rinse; and 5) treatment with an HCl solution. The pure H2SO4 solution may include an H2SO4 concentration of about ninety-eight percent (98%) or greater. After the HCl solution treatment, the cleaned surface may be a silicon surface that is free of a chemical oxide having a thickness of 5 angstroms or greater. The invention finds particular advantage in semiconductor devices that utilize multiple gate oxide thicknesses.