Gate Pad Trench Structure for SiC Withstand Voltage Reliability
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Solution Overview
Problem
Conventional silicon carbide semiconductor devices experience reliability issues in the gate pad region due to avalanche breakdown and inability to sustain withstand voltage, primarily because of concentrated electric fields at the pn interface, which is shallower than in the active region, leading to degraded reliability.
Innovation Solution
The semiconductor device incorporates trench structures and p+-type base regions in the gate pad region, ensuring that pn interfaces are at the same depth as in the active region, and providing continuous trench structures from the active to the gate pad region, with p+-type base regions underlying the trenches to prevent electric field concentration and enhance voltage withstand.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate pad region uses a conventional structure without trenches and p+-type base regions, then the device structure is simpler, but avalanche breakdown occurs and withstand voltage cannot be sustained due to concentrated electric fields at the pn interface
Solution Approach 1:
The gate pad region is segmented by introducing trench structures that divide the region into separate zones. These trenches create discrete p+-type base regions at specific locations, segmenting the electric field distribution and preventing concentration at a single pn interface point, thereby enabling withstand voltage sustenance.
Solution Approach 2:
The gate pad region is given local quality modifications by selectively introducing p+-type base regions and trenches only in the gate pad area, while maintaining the conventional structure in other regions. This localized structural enhancement addresses the specific reliability issue at the gate pad without unnecessarily complicating the entire device structure.
2Reliability
If trenches and p+-type base regions are introduced in the gate pad region, then electric field concentration is prevented and voltage withstand is enhanced, but device structure becomes more complex
Solution Approach 1:
p+-type base regions are preliminarily formed at the bottoms of the trenches in the gate pad region before final device operation. This preliminary structural preparation ensures that when voltage is applied, the electric field is already pre-configured to distribute evenly, preventing avalanche breakdown before it can occur.
Solution Approach 2:
The trench structures serve as intermediary elements between the gate electrode and the substrate. These trenches, filled with p+-type base regions, act as intermediate zones that mediate the electric field distribution, transforming the concentrated field into a distributed field and preventing direct avalanche breakdown at the pn interface.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration eliminates avalanche current concentration and ensures reliable voltage withstand in the gate pad region, enhancing the overall reliability of the semiconductor device by maintaining consistent electric field distribution across the active and gate pad regions.
Implementation Method 1
concentration of electric field at the bottoms of the trenches 116 is prevented, thereby protecting the gate insulating films 109
Implementation Method 2
experience reliability issues in the gate pad region due to avalanche breakdown and inability to sustain withstand voltage, primarily because of concentrated electric fields at the pn interface
Data Source
AI summary
A semiconductor device having an active portion and a gate pad portion on a semiconductor substrate includes: a first semiconductor layer of a first conductivity type; and a second semiconductor layer of a second conductivity type. The active portion has: first semiconductor regions of the first conductivity type; a first electrode provided on the first semiconductor regions; and first trenches. The gate pad portion has: a gate electrode pad provided above the second semiconductor layer; second trenches provided beneath the gate electrode pad; and second semiconductor regions of the second conductivity type, each provided in the first semiconductor layer so as to be in contact with a respective one of bottoms of the second trenches. Each of the second trenches is continuous with a respective one of the first trenches. The second semiconductor layer is continuous from the active portion to the gate pad portion.