3D Gate Pad Structure for Higher-Density Vertical Channel Integration
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Solution Overview
Problem
The challenge of increasing the degree of integration in semiconductor devices, particularly those with a three-dimensional structure, has not been adequately addressed, limiting their price competitiveness and performance.
Innovation Solution
The semiconductor device incorporates a gate pattern with a pad region having increased thickness, featuring a first pad region with a convex shape and a second pad region with a recessed upper surface, allowing for a stacked structure with improved integration and connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a conventional gate pattern with uniform thickness is used, then the manufacturing process is simple, but the degree of integration is insufficient
Solution Approach 1:
The gate pattern is segmented into multiple regions with different thicknesses: a first pad region, a second pad region, and a gate electrode region. This segmentation allows each region to serve specific functions while collectively achieving higher integration density without overly complicating the overall manufacturing process.
Solution Approach 2:
The gate pattern transitions from a conventional two-dimensional uniform structure to a three-dimensional multi-level structure with varying thicknesses. The first pad region extends to a first thickness, the second pad region extends to a second thickness greater than the first, and the gate electrode region has a third thickness, creating vertical dimensionality that increases integration capacity.
2Reliability
If the gate pad region thickness is increased to improve integration, then connectivity is enhanced, but manufacturing precision requirements increase
Solution Approach 1:
Different regions of the gate pattern are assigned different thickness qualities tailored to their specific functions. The first pad region has a first thickness optimized for basic connectivity, while the second pad region has a greater second thickness optimized for enhanced connectivity and integration. This local differentiation allows each region to meet its specific requirements without uniformly increasing complexity across the entire structure.
Data Source
AI summary
A semiconductor device includes a gate pattern disposed over a lower structure, and including a gate electrode region and a gate pad region extending from the gate electrode region; and a vertical channel semiconductor layer having a side surface facing the gate electrode region of the gate pattern. The gate pad region includes a first pad region having a thickness greater than a thickness of the gate electrode region. The first pad region includes an upper surface, a lower surface opposing the upper surface, and an outer side surface. The outer side surface has a lower outer side surface and an upper outer side surface, divided from each other by a boundary portion. The lower outer side surface extends from the lower surface, and a connection portion of the lower outer side surface and the lower surface has a rounded shape.