Gate Driving Panel Circuit With Buffer-Specific Bootstrapping

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Solution Overview

Problem

Existing display devices face issues with improper gate driving, leading to degraded image quality due to variations in scan output characteristics, which are not effectively addressed by modifying the scan clock signal.

Innovation Solution

A gate driving panel circuit with a structure suitable for a gate-in-panel (GIP) type, incorporating an output buffer block with scan output buffers and a logic block to control voltages, and utilizing scan pull-up and pull-down transistors with bootstrapping capacitors to stabilize signal supply, reducing scan output characteristic differences without altering the scan clock signal.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If gate driving is performed using conventional structures, then the display device can operate, but scan output characteristic variations occur leading to degraded image quality

Engineering Contradiction:
Improvegate driving stabilityVSAvoidscan output characteristic uniformity
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent applies parameter changes by adjusting the capacitance values of bootstrapping capacitors in different scan output buffers. Specifically, the capacitance of bootstrapping capacitors is varied across multiple scan output buffers to compensate for characteristic variations, thereby achieving uniform scan output characteristics without modifying the scan clock signal. This directly addresses the contradiction by changing electrical parameters to improve both reliability and manufacturing precision.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent implements local quality by providing different capacitance values for bootstrapping capacitors in different scan output buffers based on their specific position and characteristics. Each scan output buffer is locally optimized with tailored capacitor values to compensate for its particular variations, ensuring uniform overall performance while accounting for local differences in the circuit characteristics.

Inventive Principle:
Principle #3Local quality

2Manufacturing precision

If the scan clock signal is modified to reduce scan output characteristic differences, then uniformity may improve, but the complexity of signal control increases

Engineering Contradiction:
Improvescan output characteristic uniformityVSAvoidscan clock signal control
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent extracts the complexity from the scan clock signal control by removing the need to modify the scan clock signal itself. Instead, the solution is extracted to the output stage by adjusting only the bootstrapping capacitor values in the scan output buffers, thereby achieving uniformity without increasing signal control complexity. This separates the uniformity adjustment from the clock signal path.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent introduces bootstrapping capacitors as intermediary elements between the scan clock signal and the output nodes. These capacitors act as mediators that absorb and compensate for characteristic variations, allowing uniform scan output characteristics to be achieved without directly modifying the scan clock signal, thus avoiding increased signal control complexity.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Productivity

If multiple scan output buffers are used to drive gate lines, then the gate driving capability is improved, but differences in scan output characteristics arise

Engineering Contradiction:
Improvegate driving capabilityVSAvoidscan output characteristic consistency
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The patent applies parameter changes by systematically varying the capacitance values of bootstrapping capacitors across multiple scan output buffers. Each buffer's capacitor is tuned to compensate for its specific characteristics, enabling multiple buffers to work together with consistent output characteristics, thereby maintaining both high gate driving capability and uniform performance.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent implements local quality by optimizing each scan output buffer individually through tailored capacitor values. This local optimization ensures that despite the presence of multiple buffers with potentially different characteristics, each one contributes uniformly to the overall gate driving function, achieving both high productivity and consistency.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution ensures stable supply of gate signals for normal gate driving, minimizing scan output characteristic variations and enhancing image quality in display devices.

Implementation Method 1

each of the two or more scan output buffers can include a scan bootstrapping capacitor between the gate node and the source node of the scan pull-up transistor

Methodology Applied
Scientific EffectCapacitance: Capacitance

Data Source

PatentUS12567378B2Gate driving panel circuit and display device
Publication Date: 2026.03.03 LG DISPLAY CO LTD
  • US12567378B2 patent drawing
  • US12567378B2 patent drawing
  • US12567378B2 patent drawing

AI summary

A display device can include a substrate including a display area in which one or more images are displayed and a non-display area different from the display area, and a gate driving panel circuit configured to output a plurality of gate signals to a plurality of gate lines arranged in the display area. The gate driving panel circuit can include an output buffer block comprising a plurality of output buffers, wherein each of the plurality of output buffers comprising a pull-up transistor and a pull-down transistor.