Gate Pattern Formation Using Double Insulating Layers
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Solution Overview
Problem
As display devices increase in size and demand for higher resolution, the width of gate and data patterns decreases, leading to increased electric resistance and RC signal delay, which can result in poor quality due to increased thickness and potential cracking of insulating layers adjacent to the gate pattern.
Innovation Solution
A method of forming a fine metal pattern using a double gate insulating layer to cover the gate pattern, involving steps such as disposing a gate metal layer, forming photoresist patterns, etching the metal layer, and applying insulating layers to prevent cracking and signal delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the thickness of the gate pattern is increased to reduce electric resistance and RC signal delay, then the electrical performance is improved, but the taper angle of the gate pattern increases causing cracks in the insulating layer
Solution Approach 1:
The insulating layer is divided into multiple segments (first gate insulating layer and second gate insulating layer) with different thicknesses positioned at different locations. The first gate insulating layer has greater thickness at the end portion adjacent to the gate pattern, while the second gate insulating layer provides additional coverage. This segmentation allows the insulating layer to accommodate the tapered gate pattern without cracking while maintaining electrical performance.
Solution Approach 2:
Different regions of the insulating layer are given different thicknesses to match the local requirements. The first gate insulating layer has a first thickness at the end portion adjacent to the gate pattern and a second thickness at the other portion, where the first thickness is greater than the second thickness. This local quality variation prevents cracking at the critical interface with the tapered gate pattern while maintaining overall structural integrity.
2Manufacturing precision
If the width of gate and data patterns is decreased to increase resolution, then the display quality is improved, but the electric resistance increases causing RC signal delay
Solution Approach 1:
The thickness parameter of the insulating layer is changed to compensate for the reduced width of the gate pattern. By increasing the thickness of the first gate insulating layer at the end portion adjacent to the gate pattern, the structure provides better support and electrical isolation, allowing the gate pattern to maintain reduced width for high resolution while preventing signal degradation through improved insulation and structural stability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively reduces signal delay and prevents cracking of insulating layers, maintaining the quality of display apparatus by forming a fine metal pattern with controlled thickness and taper angles, ensuring stable operation.
Implementation Method 1
etching portions of the photoresist layer to form a first photo pattern
Implementation Method 2
ashing an end portion of the first photo pattern to form a second photo pattern
Data Source
AI summary
A method of forming a metal pattern includes disposing a gate metal layer on a substrate; disposing a photoresist layer on the gate metal layer; etching portions of the photoresist layer to form a first photo pattern; etching portions of the gate metal layer to form a gate pattern including a gate electrode, in which the gate metal layer is patterned using the first photo pattern as a mask; ashing an end portion of the first photo pattern to form a second photo pattern; disposing a first gate insulating layer over the substrate and the second photo pattern; removing the second photo pattern and a portion of the first gate insulating layer disposed over the second photo pattern; and disposing a second insulating layer over the gate pattern and the remaining portions of the first gate insulating layer.