Gate Pattern With Recessed Dielectric For Semiconductor Devices
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Solution Overview
Problem
Conventional semiconductor fabrication methods face issues with dopant penetration and segregation in polysilicon electrodes, leading to degraded device performance due to poly depletion and increased effective oxide layer thickness, as well as fringing field crowding in short channels, which affect on-current and transconductance.
Innovation Solution
A method involving the formation of a recess pattern in the substrate, a gate dielectric layer with stacked oxide and oxynitride layers, and a polysilicon electrode surrounded by the gate dielectric layer, which alleviates fringing field crowding and serves as an interdiffusion barrier during ion implantation, improving channel characteristics and preventing dopant penetration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ion implantation is performed on a polysilicon layer to form a polysilicon electrode, then the polysilicon electrode can be formed, but dopant penetration and segregation occur leading to degraded device performance
Solution Approach 1:
An interfacial layer is introduced between the polysilicon electrode and the gate dielectric layer to act as an intermediary barrier. This layer prevents dopant penetration into the gate dielectric and reduces dopant segregation at the polysilicon-gate dielectric interface, thereby eliminating the harmful effects while maintaining the polysilicon electrode structure.
Solution Approach 2:
The interfacial layer is formed in advance before ion implantation onto the polysilicon electrode. This preliminary action prepares a protective barrier that prevents dopant penetration during the subsequent ion implantation process, avoiding the need for post-processing corrections.
2Productivity
If the gate dielectric layer thickness is reduced to accommodate smaller device sizes, then device scaling is achieved, but poly depletion effect increases and on-current degrades
Solution Approach 1:
The interfacial layer is selectively positioned at the critical interface between the polysilicon electrode and gate dielectric, providing localized improvement in that region. This local modification addresses the poly depletion effect at the interface without requiring changes to the overall gate dielectric thickness, enabling continued device scaling while maintaining on-current performance.
3Productivity
If the gate dielectric layer thickness is reduced for device scaling, then smaller device size is achieved, but the effective oxide thickness increases due to poly depletion and transconductance degrades
Solution Approach 1:
The interfacial layer acts as a mediator that reduces the poly depletion effect at the polysilicon-gate dielectric interface. By mitigating this effect, the effective oxide thickness is reduced, which in turn improves transconductance and allows device scaling without performance degradation.
4Ease of manufacture
If conventional gate pattern fabrication is used, then the gate pattern can be formed, but fringing field crowding occurs at gate edges in short channels
Solution Approach 1:
The interfacial layer is selectively formed at the gate edge regions where fringing field crowding occurs. This localized structure modifies the electric field distribution specifically at the problematic areas without affecting the overall gate pattern fabrication process, thereby alleviating fringing field crowding while maintaining ease of manufacture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances transistor performance by reducing threshold voltage variation, improving on-current, and preventing degradation of transconductance, while addressing the short channel effect and poly depletion issues.
Implementation Method 1
Ion implantation is performed on the polysilicon layer 12
Implementation Method 2
the gate dielectric layer filling the recess pattern and protruding over the substrate, and having a groove... which serves as an interdiffusion barrier during ion implantation, improving channel characteristics and preventing dopant penetration
Implementation Method 3
the poly depletion effect resulting from overlapping gate edge fringing fields in short channels increases and contributes to degradation of device characteristics. Therefore, it is desired to alleviate such a gate edge fringing field crowding phenomenon
Data Source
AI summary
A method for fabricating a semiconductor device includes forming a recess pattern by selectively etching a substrate; forming a gate dielectric layer filling the recess pattern on the substrate; forming a groove by selectively etching the gate dielectric layer; forming a polysilicon electrode filling the groove; forming an electrode metal layer on the polysilicon electrode and the gate dielectric layer; and forming a gate pattern by etching the electrode metal layer and the gate dielectric layer. The recess pattern is formed along an edge portion of the gate pattern as a quadrilateral periphery.