Gate Pattern Silicidation Using Conductive Layer

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Solution Overview

Problem

The integration of semiconductor devices leads to increased resistance in gate patterns and word lines due to procedural limitations, such as silicon loss and impurity formation during the etch-back process, resulting in decreased program/erase rates in non-volatile memory devices and read/write rates in DRAM devices.

Innovation Solution

A method is introduced to fabricate semiconductor devices by forming a conductive layer covering the top and sidewalls of gate patterns to provide a sufficient silicon source during silicidation, using silicon epitaxial growth technology and sputtering methods to ensure uniform deposition and prevent silicon loss, thereby improving the quality of the silicide layer and reducing resistance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the upper portion of gate patterns is silicified by having the metal layer react with the upper portions of the gate patterns through thermal treatment, then the resistance of gate patterns and word lines is reduced, but the width of the gate electrode decreases due to procedural limitations

Engineering Contradiction:

Improveresistance of gate patternsVSAvoidwidth of gate electrode

Core Design Contradiction:

ReliabilityVSLength of moving object

Solution Approach 1:

The patent applies preliminary action by forming a conductive layer on the gate patterns before the silicidation process. This conductive layer serves as a silicon source that prevents width reduction during subsequent thermal treatment, ensuring the gate electrode maintains its original width while still achieving low resistance through silicidation.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The conductive layer acts as an intermediary between the gate pattern and the metal layer. It provides a controlled silicon source that reacts with the metal layer during thermal treatment, enabling silicidation without the uncontrolled silicon loss that occurs in conventional direct silicidation methods.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Area of stationary object

If the integration degree of semiconductor device is improved, then the area occupied by the semiconductor device is reduced, but the resistance of gate patterns and word lines increases

Engineering Contradiction:

Improvearea occupied by semiconductor deviceVSAvoidresistance of gate patterns

Core Design Contradiction:

Area of stationary objectVSReliability

Solution Approach 1:

The patent changes the material parameters by introducing a conductive layer with specific electrical properties. This layer has high conductivity and serves as a silicon source, allowing the gate patterns to maintain low resistance even as device dimensions are scaled down for higher integration density.

Inventive Principle:

Principle #35Parameter changes

3Ease of manufacture

If the etch-back process is performed to expose the upper portion of gate patterns, then the gate patterns can be silicified, but silicon is lost and the margins of gate pattern are damaged

Engineering Contradiction:

Improvesilicidation processVSAvoidsilicon of gate electrode

Core Design Contradiction:

Ease of manufactureVSLoss of substance

Solution Approach 1:

The conductive layer serves as a cushioning layer that compensates for silicon loss during the etch-back and silicidation processes. By providing an excess silicon source in advance, it ensures that even if some silicon is lost during processing, the gate pattern maintains adequate width and structural integrity.

Inventive Principle:

Principle #11Beforehand cushioning (Prior cushioning)

4Productivity

If the width of the upper portion of gate electrode is decreased, then the gate pattern can be formed with higher integration, but the resistance of gate electrode and surface resistance of word lines increases

Engineering Contradiction:

Improveintegration degree of semiconductor deviceVSAvoidresistance of gate electrode

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The patent uses composite materials by combining the gate electrode material with a conductive layer material that has superior electrical properties. This composite structure allows the gate pattern to achieve both high integration density and low resistance by leveraging the complementary properties of different materials.

Inventive Principle:

Principle #40Composite materials

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The method effectively increases the width of the silicified gate patterns, reduces resistance, and enhances the operation rates of semiconductor devices by providing a sufficient silicon source and improving the quality of the silicide layer, preventing inclination or breakage of gate patterns.

Implementation Method 1

using silicon epitaxial growth technology

Methodology Applied

Scientific EffectEpitaxial growth: Epitaxy

Implementation Method 2

silicifying the conductive layer and the gate patterns using the metal layer

Methodology Applied

Scientific EffectThermal treatment: Heat Treatment

Data Source

PatentUS9275904B2Method for fabricating semiconductor device

Publication Date: 2016.03.01 SK HYNIX INC

AI summary

A method for fabricating a semiconductor device, including forming gate patterns over a substrate, forming conductive layer covering top and sidewalls of each gate pattern, forming a metal layer for a silicidation process over the conductive layer, and silicifying the conductive layer and the gate patterns using the metal layer.