3D Semiconductor Gate Pick-Up Line Buffer Layer Design
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Solution Overview
Problem
The existing methods for manufacturing 3D semiconductor integrated circuits face challenges such as gate pick-up failures due to over-etching processes that can cause short circuits and voids in the gate pick-up line, particularly when forming contact holes with high aspect ratios around vertical pillars.
Innovation Solution
The solution involves forming a semiconductor integrated circuit with active pillars, buffer layers, and gates that surround the pillars, along with a gate pick-up line electrically coupled to the gates, where the gate pick-up hole is formed within the buffer layer and filled with a conductive layer, preventing the hole from extending into the substrate and reducing the aspect ratio.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If an over-etching process is used to form a contact hole for the gate pick-up line, then the contact hole can reach the gate, but the contact hole may penetrate the substrate region and cause a short circuit
Solution Approach 1:
A buffer layer is formed on the semiconductor substrate before forming the active pillar and gate structure. This buffer layer serves as a pre-prepared protective layer that prevents the etching process from penetrating through to the substrate region, thereby preventing short circuits while still allowing the contact hole to reach the gate.
Solution Approach 2:
The buffer layer acts as an intermediary layer between the gate structure and the substrate. It provides a protective barrier that mediates the etching process, allowing the contact hole to be formed through the gate region without directly exposing or damaging the underlying substrate, thus preventing short circuits.
2Reliability
If the contact hole depth approaches the pillar height to reach the gate, then the gate pick-up line can be electrically contacted, but the aspect ratio of the contact hole increases and voids may occur
Solution Approach 1:
The buffer layer is formed in advance to provide a controlled etching stop layer. This preliminary structure allows the contact hole to be formed with a controlled depth that stops at the buffer layer, preventing excessive depth and high aspect ratio issues while ensuring reliable electrical contact to the gate.
Data Source
AI summary
A 3D semiconductor integrated circuit having a gate pick-up line and a method of manufacturing the same, wherein the semiconductor integrated circuit includes a plurality of active pillars formed in a gate pick-up region, buffer layers formed on the respective active pillars in the gate pick-up region, gates each surrounding an outer circumference of the corresponding active pillar and the corresponding buffer layer, and a gate pick-up line electrically coupled to the gates.