Semiconductor Gate Pitch and S/D Depth for Mixed Transistor Layouts
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Solution Overview
Problem
The semiconductor industry faces challenges in fabricating multi-gate transistors with different constructions to meet varying design needs such as high speed, high circuit density, and low leakage, while maintaining similar processes and process windows to reduce costs and improve yield.
Innovation Solution
The integration of FinFET devices with varying gate lengths and spacings in different active areas within a semiconductor chip, allowing for the use of similar fabrication processes across different transistor types, such as NMOS and PMOS, to achieve high circuit density and speed-driven logic applications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multi-gate transistors with different constructions are fabricated to meet varying design needs, then device performance is improved, but manufacturing complexity increases
Solution Approach 1:
The patent implements different gate constructions (FinFET, MBC, GAA) in different regions of the semiconductor device according to specific design needs. Each region is tailored with appropriate transistor types: FinFETs for high-speed logic, MBC for high-density memory, and GAA for low-leakage applications. This local differentiation allows optimized device performance while managing manufacturing complexity through region-specific fabrication approaches.
Solution Approach 2:
The semiconductor device is divided into multiple active areas, each dedicated to specific transistor types with different gate constructions. The device includes first active areas with FinFETs, second active areas with MBC transistors, and third active areas with GAA transistors. This segmentation enables independent optimization of each region for its intended function while allowing standardized processing steps to be applied across regions.
2Adaptability or versatility
If different transistor constructions are used to meet design needs, then device functionality is improved, but process complexity increases
Solution Approach 1:
The patent employs a universal fabrication process that can accommodate multiple transistor types (FinFET, MBC, GAA) within the same manufacturing flow. Common process steps including substrate preparation, gate formation, and contact fabrication are applied across all transistor regions, while only specific steps are modified to create the desired gate constructions. This multi-functional approach enables different transistor functionalities to be achieved through a single standardized process platform.
Data Source
AI summary
A method of forming a semiconductor device includes doping a substrate with a dopant to form a first well region of a first circuit and a second well region of a second circuit, forming first and second active regions respectively over the first and second well regions, forming a first gate stack engaging the first active region and a second gate stack engaging the second active region, and forming a first source/drain (S/D) feature adjoining the first active region and a second S/D feature adjoining the second active region. The first gate stack has a gate pitch less than the second gate stack. The first S/D feature has a depth smaller than the second S/D feature.