Replacement Gate Dielectric Planarization to Suppress CMP Dishing
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Solution Overview
Problem
The semiconductor industry faces challenges in manufacturing three-dimensional designs like FinFETs and GAA FETs due to issues such as dishing problems during chemical-mechanical polishing (CMP) operations, which affect the planarity and isolation properties of cap insulating layers.
Innovation Solution
A method is introduced to suppress dishing problems during CMP by using specific CMP processes and slurry compositions, along with precise control of etching rates and endpoint detection techniques to ensure planarity and improve the isolation properties of cap insulating layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If chemical-mechanical polishing (CMP) is used to planarize dielectric layers, then planarity is improved, but dishing problems occur affecting cap insulating layer quality
Solution Approach 1:
The patent modifies CMP process parameters including slurry composition (pH, particle size, concentration), polishing pressure, and relative speed between polishing pad and wafer to optimize the balance between achieving planarity and preventing dishing. Specific parameters are adjusted to control the mechanical and chemical removal rates of dielectric materials.
Solution Approach 2:
The patent introduces intermediary layers (hard masks, cap insulating layers) and intermediary substances (slurry additives, cushioning layers) that mediate between the CMP process and the dielectric layers being polished. These intermediaries protect against excessive dishing while allowing planarity to be achieved.
2Manufacturing precision
If CMP process is intensified to improve planarity, then manufacturing precision increases, but dishing problems worsen
Solution Approach 1:
The patent employs periodic polishing actions with varying pressure and speed profiles during the CMP process. The polishing parameters are modulated in cycles to prevent continuous aggressive removal that causes dishing, while still achieving the required planarity over time.
Solution Approach 2:
The patent makes the CMP process dynamic by adjusting polishing pressure, speed, and slurry flow rate during the polishing operation. These dynamic adjustments allow the process to adapt to local variations in dielectric layer thickness and composition, achieving planarity without excessive dishing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enhances the planarity and isolation properties of cap insulating layers, reducing manufacturing defects and costs associated with dishing issues in FinFET and GAA FET production.
Implementation Method 1
chemical-mechanical polishing (CMP) operations
Implementation Method 2
etching rates and endpoint detection techniques
Data Source
AI summary
In a method of manufacturing a semiconductor device, a sacrificial gate structure including sacrificial gate electrode is formed over a substrate. A first dielectric layer is formed over the sacrificial gate structure. A second dielectric layer is formed over the first dielectric layer. The second and first dielectric layers are planarized and recessed, and an upper portion of the sacrificial gate structure is exposed. A third dielectric layer is formed over the exposed sacrificial gate structure and over the first dielectric layer. A fourth dielectric layer is formed over the third dielectric layer. The fourth and third dielectric layers are planarized, and the sacrificial gate electrode is exposed and part of the third dielectric layer remains on the recessed first dielectric layer. The recessing the first dielectric layer comprises a first etching operation and a second etching operation using a different etching as from the first etching operation.