Gate Plug and Dual Work Function Word Line Structure for GIDL Reduction
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Solution Overview
Problem
The miniaturization of semiconductor devices leads to issues like gate-induced drain leakage (GIDL) between adjacent components, affecting the performance of dynamic random access memory (DRAM), which existing technologies have not adequately addressed.
Innovation Solution
The use of a first and second liner as etch stop layers during the etching process in forming a semiconductor structure, along with a gate plug in contact with dual work function word lines, to reduce etching damage and improve electrical properties and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the size of semiconductor devices is reduced to increase integration, then productivity and integration are improved, but gate-induced drain leakage between adjacent components increases
Solution Approach 1:
The patent applies segmentation by dividing the etching protection into multiple distinct layers: a first liner layer and a second liner layer with different materials and etching selectivities. This segmented approach allows selective protection of different components during sequential etching operations, preventing harmful interactions between adjacent miniaturized components while maintaining high integration density.
Solution Approach 2:
The patent implements local quality by assigning different material compositions and etching resistance properties to different liner layers at different locations. The first liner layer provides protection for certain components while the second liner layer protects other components, allowing each region to have optimized etching resistance tailored to its specific requirements, thereby preventing GIDL in miniaturized structures.
2Ease of manufacture
If conventional etching processes are used in miniaturized devices, then manufacturing simplicity is maintained, but etching damage to adjacent components increases
Solution Approach 1:
The etching process is segmented into multiple selective etching steps, each protected by appropriate liner layers. This segmentation allows conventional etching processes to be applied sequentially with different selectivities, maintaining manufacturing simplicity while significantly reducing etching damage to adjacent components through the protective liner structure.
Solution Approach 2:
The liner layers serve as intermediary protective barriers between the etching process and the components being etched. These intermediary layers with different etching selectivities allow the etching process to proceed without directly damaging sensitive components, thereby improving reliability while maintaining process simplicity.
3Reliability
If gate plug contact area with word line is increased, then controllability is improved, but device complexity increases
Solution Approach 1:
The word line structure is segmented into multiple work function layers with different materials, and the gate plug is designed to contact specific layers. This segmentation increases the effective contact area and improves controllability without requiring a complete redesign of the device structure, as the multi-layer approach integrates smoothly with existing fabrication processes.
Solution Approach 2:
The patent uses composite material structures with multiple work function layers having different material compositions. This composite approach increases the gate plug contact area and improves controllability by allowing selective contact with layers having appropriate work functions, while the modular nature of composite materials keeps device complexity manageable.
Data Source
AI summary
A semiconductor structure and a method of forming the same are provided. The semiconductor structure includes a first work function layer, a second work function layer, a protective layer, a gate stack, a first liner, a second liner, a planarization layer, and a gate plug. The first work function layer is disposed on a substrate. The second work function layer is disposed on the first work function layer. The protective layer is disposed on the second work function layer. The gate stack is disposed on the protective layer. The first liner is disposed on the gate stack. The second liner is disposed on the first liner. The planarization layer is disposed on the second liner. The gate plug is disposed on the planarization layer and in contact with the first work function layer and the second work function layer.